Method for programming memory device, memory device and memory system
The present disclosure provides a programming method, a memory device and a memory system. The method includes, based on coupling offsets, dividing target programmed states into N groups, each group corresponding to a different first programmed state, wherein an i-th group has K i number of different target programmed states and corresponds to an i-th first programmed state. At least two groups of target programmed states have two different numbers of target programmed states. The method also includes performing a first program operation to program memory cells to respective first programmed states; and performing a second program operation to program an i-th group of memory cells at the i-th first programmed state to K i number of different target programmed states.
1 . A method for programming a memory device, comprising:
performing a first program operation on memory cells to be programmed such that each of the memory cells is programmed to a respective one of N different first programmed states, wherein:
N is a positive integer greater than 1 and less than M; and
M is a total number of target programmed states of the memory cells; performing a second program operation to program an i-th group of the memory cells at an i-th first programmed state to K i number of different target programmed states, wherein:
K i is greater than or equal to 1 and less than N;
i is greater than or equal to 1, and less than or equal to N; and
at least two first programmed states correspond to different K i values; and
grouping adjacent target programmed states in a same group when coupling offsets of the adjacent target programmed states are within a predetermined range.
2 . The method of claim 1 , further comprising:
dividing the target programmed states into N groups that correspond to the N different first programmed states based on the coupling offsets of the target programmed states during the programming, wherein an i-th group of the target programmed states has the K i number of the target programmed states.
3 . The method of claim 2 , wherein the performing of the first program operation comprises performing the first program operation according to the N groups of target programmed states, wherein each of the memory cells is programmed to the respective one of the N different first programmed states according to the N groups.
4 . The method of claim 3 , further comprising:
grouping a first group of adjacent target programmed states, whose coupling offsets are less than a first preset threshold value, into the first group;
grouping a second group of adjacent target programmed states, whose coupling offsets are greater than or equal to the first preset threshold value but less than a second preset threshold value, into the second group; and
grouping a third group of adjacent target programmed states, whose coupling offsets are greater than or equal to the second preset threshold value, into the third group.
5 . The method of claim 2 , further comprising:
determining the coupling offsets of the target programmed states by measuring changes of threshold voltages of memory cells coupled to a selected word line influenced by threshold voltages of memory cells coupled to an adjacent word line.
6 . The method of claim 1 , further comprising:
after performing the first program operation, performing a first verification operation to determine whether each of the memory cells is programmed to the respective one of N different first programmed states.
7 . The method of claim 6 , further comprising:
performing the first program operation on the memory cells during each of one or more loops;
after each of the one or more loops, determining whether to proceed to a next loop according to results of the first verification operation;
stopping the first program operation if the results show that the memory cells pass the first verification operation; and
proceeding to the next loop until each of the memory cells is programmed to the respective one of N different first programmed states.
8 . The method of claim 6 , further comprising:
verifying the N different first programmed states using N different first verification voltages.
9 . The method of claim 6 , further comprising:
after performing the second program operation, performing a second verification operation to determine whether each of the memory cells is programmed to a respective target programmed state, wherein different second verification voltages are used to verify the K i number of different target programmed states.
10 . The method of claim 9 , wherein an i-th first verification voltage used to verify the i-th first programmed state is smaller than any of the second verification voltages used to verify the K i number of target programmed states in the i-th group.
11 . A memory device, comprising:
a memory array comprising memory cells; and
a peripheral circuit coupled to the memory array and configured to:
perform a first program operation on the memory cells to be programmed such that each of the memory cells is programmed to a respective one of N different first programmed states, wherein:
N is a positive integer greater than 1 and less than M; and
M is a total number of target programmed states of the memory cells;
perform a second program operation to program an i-th group of the memory cells at an i-th first programmed state to K i number of the target programmed states, wherein:
K i is greater than or equal to 1 and less than N;
i is greater than or equal to 1, and less than or equal to N; and
at least two first programmed states correspond to different K i values; and
group adjacent target programmed states in a same group when coupling offsets of the adjacent target programmed states are within a predetermined range.
12 . The memory device of claim 11 , wherein the peripheral circuit is further configured to:
divide the target programmed states into N groups that correspond to the N different first programmed states based on the coupling offsets of the target programmed states during the programming, wherein an i-th group of the target programmed states has the K i number of the target programmed states.
13 . The memory device of claim 12 , wherein the performing of the first program operation comprises performing the first program operation according to the N groups of target programmed states, wherein each of the memory cells is programmed to the respective one of the N different first programmed states according to the N groups.
14 . The memory device of claim 13 , wherein the peripheral circuit is further configured to:
group a first group of adjacent target programmed states, whose coupling offsets are less than a first preset threshold value, into the first group;
group a second group of adjacent target programmed states, whose coupling offsets are greater than or equal to the first preset threshold value but less than a second preset threshold value, into the second group; and
group a third group of adjacent target programmed states, whose coupling offsets are greater than or equal to the second preset threshold value, into the third group.
15 . The memory device of claim 12 , wherein the peripheral circuit is further configured to:
determine the coupling offsets of the target programmed states by measuring changes of threshold voltages of memory cells coupled to a selected word line influenced by threshold voltages of memory cells coupled to an adjacent word line.
16 . The memory device of claim 11 , wherein the peripheral circuit is further configured to:
after performing the first program operation, perform a first verification operation to determine whether each of the memory cells is programmed to the respective one of N different first programmed states.
17 . The memory device of claim 16 , wherein the peripheral circuit is further configured to:
perform the first program operation on the memory cells during each of one or more loops;
after each of the one or more loops, determine whether to proceed to a next loop according to results of the first verification operation;
stop the first program operation if the results show that the memory cells pass the first verification operation; and
proceed to the next loop until each of the memory cells is programmed to the respective one of N different first programmed states.
18 . The memory device of claim 16 , wherein the peripheral circuit is further configured to:
verify the N different first programmed states using N different first verification voltages.
19 . The memory device of claim 16 , wherein the peripheral circuit is further configured to:
after performing the second program operation, perform a second verification operation to determine whether each of the memory cells is programmed to a respective target programmed state, wherein different second verification voltages are used to verify the K i number of different target programmed states.
20 . The memory device of claim 19 , wherein an i-th first verification voltage used to verify the i-th first programmed state is smaller than any of the second verification voltages used to verify the K i number of target programmed states in the i-th group.