Thermally enhanced chip-on-wafer or wafer-on-wafer bonding
Semiconductor packages including an integrated heat spreader and methods of fabrication are described. In an embodiment, a semiconductor package includes a first package level, a second package level including one or more second-level chiplets, and a heat spreader bonded to the second package level with a metallic layer, which may include one or more intermetallic compounds formed by transient liquid phase bonding.
1 . A semiconductor package comprising:
a first package level;
a second package level including one or more second-level chiplets;
a heat spreader bonded to the second package level with a metallic layer; and
straight package sidewalls spanning the first package level, the second package level, the metallic layer, and the heat spreader;
wherein the metallic layer comprises:
a first element selected from the group consisting of Cu, Al, Ag, and Au; and
a second element selected from the group consisting of In and Sn, and the second element is completely contained within one or more intermetallic compounds.
2 . The semiconductor package of claim 1 , wherein the heat spreader is a silicon substrate.
3 . The semiconductor package of claim 1 , wherein the first package level and the second package level are hybrid bonded to one another.
4 . The semiconductor package of claim 1 , wherein the one or more second-level chiplets is hybrid bonded to the first package level.
5 . The semiconductor package of claim 1 , further comprising an interposer between the first package level and the second package level.
6 . The semiconductor package of claim 5 , wherein the interposer is hybrid bonded with the first package level.
7 . The semiconductor package of claim 6 , wherein the second package level is hybrid bonded with the interposer.
8 . The semiconductor package of claim 1 , wherein the first package level comprises an interposer.
9 . The semiconductor package of claim 1 , wherein the first package level comprises a single first-level chiplet.
10 . The semiconductor package of claim 1 , wherein the first package level comprises a plurality of first-level chiplets.
11 . The semiconductor package of claim 1 , wherein
the one or more second-level chiplets is embedded in a multiple layer gap fill including a bulk gap fill material and a capping gap fill material comprising silicon; and
the heat spreader is a silicon substrate.
12 . The semiconductor package of claim 1 , further comprising an interposer between the first package level and the second package level, wherein the one or more second-level chiplets is hybrid bonded with the interposer, and the first package level comprises one or more first-level chiplets hybrid bonded with the interposer.
13 . The semiconductor package of claim 12 , wherein the heat spreader comprises a silicon substrate, and the interposer comprises a bulk layer formed of a material selected from the group consisting of silicon and glass.
14 . The semiconductor package of claim 1 , wherein the first package level comprises an interposer with a bulk layer formed of a material selected from the group consisting of silicon and glass, and the one or more second-level chiplets is hybrid bonded with the interposer.
15 . The semiconductor package of claim 2 , wherein the one or more intermetallic compounds comprises the first element and the second element.
16 . The semiconductor package of claim 2 , wherein the one or more second-level chiplets is a plurality of second level chiplets.
17 . The semiconductor package of claim 16 , wherein the plurality of second-level chiplets is embedded in a gap fill material, and the metallic layer spans over and is in direct contact with the gap fill material and the plurality of second-level chiplets.
18 . The semiconductor package of claim 17 , wherein the one or more intermetallic compounds is in direct contact with the heat spreader and the plurality of second-level chiplets.
19 . The semiconductor package of claim 18 , wherein the gap fill material is an organic molding compound material or SiN.
20 . The semiconductor package of claim 18 , wherein the metallic layer comprises a top metal bonding layer directly on the heat spreader, a bottom metal bonding layer directly on the plurality of second-level chiplets and the gap fill material, and a layer of the one or more intermetallic compounds between the top metal bonding layer and the bottom metal bonding layer.