Semiconductor package including substrate having a dummy pattern between pads
A semiconductor package includes a redistribution substrate having first and second surfaces, and an insulating member and a plurality of redistribution layers on different levels in the insulating member and electrically connected together; a plurality of under bump metallurgy (UBM) pads in the insulating member and connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the first surface, the UBM pads having a lower surface exposed to the first surface of the redistribution substrate; a dummy pattern between the UBM pads in the insulating member, the dummy pattern having a lower surface located at a level higher than the lower surface of the UBM pads; and at least one semiconductor chip on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the second surface.
1 . A semiconductor package, comprising:
a redistribution substrate having first and second surfaces, disposed opposite to each other, the redistribution substrate including an insulating member and a plurality of redistribution layers disposed at a plurality of different levels in the insulating member, respectively, and electrically connected to each other;
a plurality of under-bump metallurgy (UBM) pads disposed in the insulating member and electrically connected to a redistribution layer, among the plurality of redistribution layers, that is adjacent to the first surface of the redistribution substrate, the plurality of UBM pads having lower surfaces with respect to the first surface of the redistribution substrate;
a dummy pattern disposed between the plurality of UBM pads in the insulating member, the dummy pattern having a lower surface located at a level higher than the lower surfaces of the plurality of UBM pads;
a plurality of external connection conductors disposed on the lower surfaces of the plurality of UBM pads respectively, and
at least one semiconductor chip disposed on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer, among the plurality of redistribution layers, adjacent to the second surface of the redistribution substrate, wherein:
the insulating member includes a first insulating film covering a first portion of a side surface of each of the plurality of UBM pads, the first portion adjacent the first surface of the redistribution substrate, and a second insulating film covering a second portion of the side surface of each of the plurality of UBM pads, the second portion above the first portion,
the first portion is spaced apart from the first insulating film,
the second portion is in direct contact with the second insulating film, and
the semiconductor package further comprises a UBM seed layer disposed between the first portion and the first insulating film, and disposed between the lower surface of each of the plurality of UBM pads and each of the plurality of external connection conductors.
2 . The semiconductor package as claimed in claim 1 , wherein the dummy pattern is disposed on the first insulating film, and has a side surface covered by the second insulating film.
3 . The semiconductor package as claimed in claim 2 , wherein the side surface of the dummy pattern is in direct contact with the second insulating film.
4 . The semiconductor package as claimed in claim 2 , wherein a dummy seed layer is disposed between the lower surface of the dummy pattern and the first insulating film.
5 . The semiconductor package as claimed in claim 1 , wherein the dummy pattern is spaced by a distance of 30 μm or less from an adjacent UBM pad, among the plurality of UBM pads.
6 . The semiconductor package as claimed in claim 1 , wherein the dummy pattern is spaced by a distance of 2 μm or more from the first surface of the redistribution substrate.
7 . The semiconductor package as claimed in claim 1 , wherein the plurality of UBM pads have respective thicknesses that are greater than a thickness of the redistribution layer connected thereto.
8 . The semiconductor package as claimed in claim 1 , wherein a portion of each of the plurality of UBM pads protrudes from the first surface of the redistribution substrate.
9 . The semiconductor package as claimed in claim 1 , wherein the insulating member includes a photoimageable dielectric (PID) material.
10 . The semiconductor package as claimed in claim 1 , wherein:
the plurality of redistribution layers include a redistribution via connecting redistribution layers disposed at adjacent levels, and
the redistribution via has a shape narrowed in a direction of the first surface of the redistribution substrate from the second surface of the redistribution substrate.
11 . The semiconductor package as claimed in claim 1 , further comprising a molding portion disposed on the second surface of the redistribution substrate, and surrounding the at least one semiconductor chip.
12 . The semiconductor package as claimed in claim 11 , further comprising a heat dissipation member disposed on the at least one semiconductor chip and the molding portion.
13 . A semiconductor package, comprising:
a redistribution substrate having first and second surfaces, disposed opposite to each other, and including a plurality of insulating layers and a plurality of redistribution layers in the plurality of insulating layers, respectively, and electrically connected to each other;
a plurality of under-bump metallurgy (UBM) pads disposed in the plurality of insulating layers and electrically connected to the plurality of redistribution layers, the plurality of UBM pads having lower surfaces with respect to the first surface of the redistribution substrate;
a dummy pattern disposed between the plurality of UBM pads in the plurality of insulating layers, the dummy pattern having a lower surface located at a level higher than the lower surfaces of the plurality of UBM pads; and
at least one semiconductor chip disposed on the second surface of the redistribution substrate and electrically connected to the plurality of redistribution layers, wherein:
the lower surface of the dummy pattern is spaced apart from the plurality of insulating layers by a seed layer for the dummy pattern, and
a side surface of the dummy pattern is in direct contact with an insulating film.
14 . The semiconductor package as claimed in claim 13 , wherein the seed layer for the dummy pattern is not present between the side surface of the dummy pattern and the insulating film.
15 . A semiconductor package, comprising:
a redistribution substrate having first and second surfaces, disposed opposite to each other, and including a plurality of insulating layers and a plurality of redistribution layers in the plurality of insulating layers, respectively, and electrically connected to each other;
a plurality of under-bump metallurgy (UBM) pads disposed in the plurality of insulating layers and electrically connected to the plurality of redistribution layers, the plurality of UBM pads having lower surfaces with respect to the first surface of the redistribution substrate;
a dummy pattern disposed between the plurality of UBM pads in the plurality of insulating layers, the dummy pattern having a lower surface located at a level higher than the lower surfaces of the plurality of UBM pads;
at least one semiconductor chip disposed on the second surface of the redistribution substrate and electrically connected to the plurality of redistribution layers;
first seed layers extending along side surfaces of the plurality of UBM pads; and
second seed layers extending along the lower surface of the dummy pattern,
wherein a first length of each of the first seed layers is shorter than a length of the respective side surfaces of the plurality of UBM pads, wherein the first length of each of the first seed layers and the length of the respective side surfaces are in a direction from the first surface of the redistribution substrate toward the second surface of the redistribution substrate.
16 . The semiconductor package as claimed in claim 15 , wherein a second length of each of the second seed layers is equal to a length of the lower surface of the dummy pattern, wherein the second length of each of the second seed layers and the length of the lower surface of the dummy pattern are in the direction from the first surface of the redistribution substrate toward the second surface of the redistribution substrate.