IP Library Granted Patent US 12,469,793
Granted Patent B2
US 12,469,793 · App. 17/722,689 · Granted Nov 11, 2025

Core substrate, package structure including the core substrate, and method of manufacturing semiconductor package

Inventors: Myeongho Hong (Suwon-si, KR); Dowon Kim (Anyang-si, KR); Jangbae Son (Incheon, KR); Seokwoo Yoon (Cheonan-si, KR); Kyomuk Lim (Sejong-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L23/5389H01L21/4857H01L21/486H01L21/565H01L23/3121H01L23/3128H01L23/49816H01L23/49822H01L23/49838H01L23/5383H01L23/5386H01L24/02H01L24/08H01L24/19H01L24/95H05K1/185H01L21/561H01L21/568H01L22/34H01L23/5381H01L25/0655H01L2224/02331H01L2224/02333H01L2224/02371H01L2224/04105H01L2224/08235H01L2224/12105H01L2924/1815
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Quick Facts
Patent No.
US 12,469,793
App. No.
17/722,689
Granted
Nov 11, 2025
Kind
B2
Abstract

A package structure includes a core substrate including a substrate base including a plurality of first cavities and a plurality of second cavities, a plurality of blocks in the plurality of second cavities; and a plurality of bridge structures that extend between each of the plurality of blocks and the substrate base, a plurality of semiconductor chips in the plurality of first cavities, and a molding layer configured to cover the core substrate and the plurality of semiconductor chips, a portion of the molding layer being in the plurality of first cavities and the plurality of second cavities.

Claims (54)

1 . A package structure comprising:

a core substrate including a substrate base including a plurality of first cavities and a plurality of second cavities, a plurality of blocks in the plurality of second cavities, and a plurality of bridge structures in the plurality of second cavities and extending between each block of the plurality of blocks and the substrate base;

a plurality of semiconductor chips in the plurality of first cavities; and

a molding layer covering the core substrate and the plurality of semiconductor chips, a portion of the molding layer is in the plurality of first cavities and the plurality of second cavities, wherein each bridge structure is in a portion of the second cavity between each block and the substrate base and the molding layer is in a remaining portion of the second cavity between each block and the substrate base.

2 . The package structure of claim 1 , wherein the substrate base, the plurality of blocks, and the plurality of bridge structures include a same material as each other.

3 . The package structure of claim 1 , wherein each first cavity of the plurality of first cavities, each second cavity of the plurality of second cavities, and each block of the plurality of blocks have a quadrangular shape,

a horizontal width of each first cavity of the plurality of first cavities in a first horizontal direction is equal to a horizontal width of each second cavity of the plurality of second cavities in the first horizontal direction, and

the first horizontal direction is parallel to a sidewall of the substrate base and an upper surface of the substrate base.

4 . The package structure of claim 3 , wherein each block of the plurality of blocks is connected to the substrate base through one or more of the plurality of bridge structures.

5 . The package structure of claim 3 , wherein each block of the plurality of blocks includes a first edge and a second edge opposite to each other, and

each block of the plurality of blocks is connected to the substrate base through at least one first bridge structure that extends between the first edge and the substrate base and at least one second bridge structure that extends between the second edge and the substrate base.

6 . The package structure of claim 1 , wherein a horizontal width of each block of the plurality of blocks in a first horizontal direction is equal to a horizontal width of each semiconductor chip of the plurality of semiconductor chips in the first horizontal direction, and

the first horizontal direction is parallel to a sidewall of the substrate base and an upper surface of the substrate base.

7 . The package structure of claim 1 , wherein a horizontal width of each block of the plurality of blocks in a first horizontal direction is different from a horizontal width of each semiconductor chip of the plurality of semiconductor chips in the first horizontal direction, and

wherein the first horizontal direction is parallel to a sidewall of the substrate base and an upper surface of the substrate base.

8 . The package structure of claim 1 , wherein a distance between each block of the plurality of blocks and the substrate base ranges from 20 μm to 1000 μm.

9 . The package structure of claim 1 , wherein the plurality of blocks include

at least one first block having a first horizontal width in a first horizontal direction; and

at least one second block having a second horizontal width that is different from the first horizontal width in the first horizontal direction,

wherein the first horizontal direction is parallel to a sidewall of the substrate base and an upper surface of the substrate base.

10 . The package structure of claim 1 , wherein the plurality of first cavities are provided in a central portion of the substrate base, and

the plurality of second cavities are provided in an outer portion of the substrate base.

11 . The package structure of claim 1 , wherein a first region of the substrate base in which the plurality of first cavities are provided is surrounded by a second region of the substrate base in which the plurality of second cavities are provided.

12 . The package structure of claim 1 , further comprising:

a lower redistribution structure that includes a conductive lower redistribution pattern on a lower surface of the core substrate and lower surfaces of the plurality of semiconductor chips and electrically connected to a chip pad of each of the plurality of semiconductor chips.

13 . The package structure of claim 12 , wherein the core substrate further includes a conductive connection structure extending from a lower surface of the substrate base to an upper surface of the substrate base, and

wherein the package structure further includes an upper redistribution structure that includes a conductive upper redistribution pattern on an upper surface of the core substrate and upper surfaces of the plurality of semiconductor chips and electrically connected to the conductive lower redistribution pattern through the conductive connection structure of the core substrate.

14 . A package structure comprising:

a core substrate including a substrate base that includes a plurality of first cavities and a plurality of second cavities, a plurality of blocks in the plurality of second cavities, and a plurality of bridge structures that extend between each of the plurality of blocks and the substrate base;

a plurality of semiconductor chips in the plurality of first cavities; and

a molding layer that covers the core substrate and the plurality of semiconductor chips, a portion of the molding layer is in the plurality of first cavities and the plurality of second cavities,

wherein the substrate base, the plurality of blocks, and the plurality of bridge structures include a same material as each other,

each of the plurality of blocks has a quadrangular shape in a plan view, and

the plurality of bridge structures include at least one first bridge structure that extends from a first edge of each of the plurality of blocks to the substrate base and at least one second bridge structure that extends from a second edge of each of the plurality of blocks to the substrate base.

15 . The package structure of claim 14 , wherein the core substrate further includes a conductive connection structure that extends from a lower surface of the substrate base to an upper surface of the substrate base within the substrate base, and

wherein the package structure further comprises:

a lower redistribution structure that includes a conductive lower redistribution pattern on a lower surface of the core substrate and lower surfaces of the plurality of semiconductor chips and electrically connected to a chip pad of each of the plurality of semiconductor chips; and

an upper redistribution structure that includes a conductive upper redistribution pattern on an upper surface of the core substrate and upper surfaces of the plurality of semiconductor chips and electrically connected to the conductive lower redistribution pattern through the conductive connection structure of the core substrate.

16 . A core substrate comprising:

a substrate base in a quadrangular panel shape that includes a plurality of first cavities and a plurality of second cavities;

a plurality of blocks in the plurality of second cavities; and

a plurality of bridge structures that extends between each of the plurality of blocks and the substrate base, wherein the plurality of first cavities are in a central portion of the substrate base, and the plurality of second cavities are in an outer portion of the substrate base and surrounding the plurality of first cavities.

17 . The core substrate of claim 16 , wherein the substrate base, the plurality of blocks, and the plurality of bridge structures include a same material as each other.

18 . The core substrate of claim 16 , wherein each of the plurality of first cavities and each of the plurality of second cavities extend from an upper surface of the substrate base to a lower surface of the substrate base to pass through the substrate base,

each of the plurality of first cavities, each of the plurality of second cavities, and each of the plurality of blocks have a quadrangular shape,

a horizontal width of each first cavity of the plurality of first cavities in a first horizontal direction is equal to a horizontal width of each second cavity of the plurality of second cavities in the first horizontal direction, and

the first horizontal direction is parallel to a sidewall of the substrate base and upper surface of the substrate base.

19 . The core substrate of claim 16 , wherein the plurality of blocks include:

at least one first block having a first horizontal width in a first horizontal direction; and

at least one second block having a second horizontal width in the first horizontal direction,

wherein the second horizontal width is different from the first horizontal width, and

wherein the first horizontal direction is parallel to a sidewall of the substrate base and an upper surface of the substrate base.

20 . The core substrate of claim 16 , further comprising:

a conductive connection structure in the substrate base and that extends from a lower surface of the substrate base to an upper surface of the substrate base.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2022
From: HONG, MYEONGHO; KIM, DOWON; SON, JANGBAE; YOON, SEOKWOO; LIM, KYOMUK
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 059760/0823 →
Priority Claims (1)
KR 10-2021-0111203 · Aug 23, 2021 · national
Continuity (1)
Related Publication 20230057039A1 · Feb 23, 2023
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