Support structure to reinforce stacked semiconductor wafers
Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes bonding a first semiconductor wafer to a second semiconductor wafer. A bond interface is disposed between the first and second semiconductor wafers. The first semiconductor wafer has a peripheral region laterally surrounding a central region. A support structure is formed between a first outer edge of the first semiconductor wafer and a second outer edge of the second semiconductor wafer. The support structure is disposed within the peripheral region. A thinning process is performed on the second semiconductor wafer.
1 . A method for forming a semiconductor structure, comprising:
bonding a first semiconductor wafer to a second semiconductor wafer, wherein a bond interface is disposed between the first and second semiconductor wafers, wherein the first semiconductor wafer has a peripheral region laterally surrounding a central region;
forming a support structure between a first outer edge of the first semiconductor wafer and a second outer edge of the second semiconductor wafer, wherein the support structure is disposed within the peripheral region, wherein the support structure comprises an inner segment between the first semiconductor wafer and the second semiconductor wafer, wherein the support structure is laterally offset from an outermost point of the first outer edge by a lateral distance that is greater than a vertical thickness of the inner segment; and
performing a thinning process on the second semiconductor wafer.
2 . The method of claim 1 , wherein a lower surface of the support structure conforms to a rounded shape of the first outer edge and an upper surface of the support structure conforms to a rounded shape of the second outer edge.
3 . The method of claim 1 , wherein the support structure is deposited as a liquid and a curing process is performed before the thinning process to harden the support structure.
4 . The method of claim 3 , wherein the curing process reaches a temperature within a range of about 200 to 420 degrees Celsius.
5 . The method of claim 1 , wherein the thinning process removes at least a portion of the support structure, wherein a top surface of the support structure is co-planar with a top surface of the second semiconductor wafer.
6 . The method of claim 1 , wherein the support structure is formed after bonding the first semiconductor wafer to the second semiconductor wafer, and wherein the support structure directly contacts at least a portion of the bond interface.
7 . The method of claim 1 , further comprising:
bonding a third semiconductor wafer to the second semiconductor wafer, wherein an upper bond interface is disposed between the second semiconductor wafer and the third semiconductor wafer;
forming an upper support structure between the second outer edge of the second semiconductor wafer and a third outer edge of the third semiconductor wafer; and
performing a second thinning process on the third semiconductor wafer.
8 . The method of claim 7 , wherein a trimming process is not performed on the second semiconductor wafer and the third semiconductor wafer.
9 . A method for forming an integrated chip, comprising:
forming a first plurality of semiconductor devices over a central region of a first semiconductor wafer;
bonding a second semiconductor wafer to the first semiconductor wafer, wherein a bond interface is disposed between the first and second semiconductor wafers, wherein the first semiconductor wafer has a first rounded edge and the second semiconductor wafer has a second rounded edge;
forming a support structure between the first rounded edge and the second rounded edge, wherein the support structure is ring-shaped and laterally encloses the central region, wherein the support structure conforms to a shape of a first notch of the first semiconductor wafer, and wherein the support structure is disposed between the first notch of the first semiconductor wafer and a second notch of the second semiconductor wafer; and
reducing a thickness of the second semiconductor wafer after forming the support structure.
10 . The method of claim 9 , further comprising:
forming a first interconnect structure and a first dielectric structure on the first semiconductor wafer;
forming a second plurality of semiconductor devices on the second semiconductor wafer; and
forming a second interconnect structure and a second dielectric structure on the second semiconductor wafer, wherein the first dielectric structure contacts the second dielectric structure at the bond interface, wherein the support structure continuously extends from a first rounded edge of the first dielectric structure to a second rounded edge of the second dielectric structure.
11 . The method of claim 10 , wherein the support structure comprises a conductive material different from a dielectric material of the first and second dielectric structures.
12 . The method of claim 10 , wherein a width of the support structure is greater than a width of the second rounded edge of the second dielectric structure.
13 . The method of claim 10 , wherein reducing the thickness of the second semiconductor wafer removes portions of the second dielectric structure and portions of the support structure, wherein a top surface of the second dielectric structure and a top surface of the support structure are co-planar.
14 . The method of claim 10 , wherein forming the support structure comprises:
forming a lower support structure on the first rounded edge of the first dielectric structure; and
forming an upper support structure on the second rounded edge of the second dielectric structure, wherein the lower support structure directly contacts the upper support structure along the bond interface.
15 . The method of claim 9 , wherein a width of the support structure continuously increases from the bond interface in a direction away from the central region.
16 . The method of claim 9 , wherein the support structure is formed by chemical vapor deposition, physical vapor deposition, or electro-chemical plating.
17 . The method of claim 9 , wherein reducing the thickness of the second semiconductor wafer reduces a diameter of the second semiconductor wafer, wherein the diameter of the second semiconductor wafer is less than a diameter of the first semiconductor wafer.
18 . A method for forming an integrated chip, comprising:
bonding a first semiconductor wafer to a second semiconductor wafer, wherein the first semiconductor wafer comprises a first rounded edge, wherein the second semiconductor wafer comprises a second rounded edge and a third rounded edge above the second rounded edge, wherein the first rounded edge faces the second rounded edge;
forming a support structure between the first semiconductor wafer and the second semiconductor wafer, wherein the support structure continuously vertically extends from the first rounded edge to the second rounded edge, wherein a height of the support structure continuously increases from an interface between the first and second semiconductor wafers in a first direction away from a center of the first semiconductor wafer, wherein an outer sidewall of the support structure is curved in a second direction towards the interface; and
performing a thinning process on the second semiconductor wafer, wherein the thinning process removes the third rounded edge of the second semiconductor wafer, and wherein after the thinning process a top surface of the support structure is co-planar with a top surface of the second semiconductor wafer.
19 . The method of claim 18 , further comprising:
forming a plurality of semiconductor devices over a center region of the second semiconductor wafer, wherein the support structure laterally encloses the center region; and
wherein the first semiconductor wafer directly contacts the second semiconductor wafer at the interface.
20 . The method of claim 18 , wherein the support structure comprises a metal.