Semiconductor package
A semiconductor package includes a lower semiconductor chip and semiconductor chips in a stack on the lower semiconductor chip in a first direction perpendicular to a top surface of the lower semiconductor chip. Connection bumps are between the lower semiconductor chip and a bottommost one of the semiconductor chips and between the semiconductor chips, A protection layer covers a lateral surface of each of the connection bumps. A mold layer is on the lower semiconductor chip and covering lateral surfaces of the semiconductor chips. The mold layer extends between the bottommost one of the semiconductor chips and the lower semiconductor chip and between the semiconductor chips. The protection layer is between the mold layer and the lateral surface of each of the connection bumps.
1 . A semiconductor package, comprising:
a lower semiconductor chip;
a plurality of semiconductor chips in a stack on the lower semiconductor chip in a first direction perpendicular to a top surface of the lower semiconductor chip;
a plurality of connection bumps between the lower semiconductor chip and a bottommost one of the plurality of semiconductor chips, and the plurality of connection bumps being between the plurality of semiconductor chips;
a protection layer that covers a lateral surface of each of the plurality of connection bumps; and
a mold layer on the lower semiconductor chip, the mold layer covering lateral surfaces of the plurality of semiconductor chips,
wherein the mold layer extends between the bottommost one of the plurality of semiconductor chips and the lower semiconductor chip, and the mold layer extends between the plurality of semiconductor chips,
wherein the protection layer is between the mold layer and the lateral surface of each of the plurality of connection bumps,
wherein each of the plurality of semiconductor chips has a top surface and a bottom surface that are opposite to each other in the first direction, and
the protection layer extends between the mold layer and the top surface of each of the plurality of semiconductor chips, and the protection layer extends between the mold layer and the bottom surface of each of the plurality of semiconductor chips.
2 . The semiconductor package of claim 1 , wherein the protection layer is in contact with the lateral surface of each of the plurality of connection bumps.
3 . The semiconductor package of claim 2 , wherein the protection layer is in contact with the mold layer.
4 . The semiconductor package of claim 1 , wherein the mold layer extends with no boundary from the lateral surfaces of the plurality of semiconductor chips toward a space between the bottommost one of the plurality of semiconductor chips and the lower semiconductor chip, and the mold layer extends between the plurality of semiconductor chips.
5 . The semiconductor package of claim 1 , wherein the mold layer defines at least one void between the bottommost one of the plurality of semiconductor chips and the lower semiconductor chip or between the plurality of semiconductor chips.
6 . The semiconductor package of claim 1 , wherein
the protection layer includes a self-assembled monolayer,
the self-assembled monolayer includes a hydrocarbon chain, a first reaction group connected to one end of the hydrocarbon chain, and a second reaction group connected to an opposite end of the hydrocarbon chain, and
the first reaction group chemically adsorbs the self-assembled monolayer to the lateral surface of each of the plurality of connection bumps.
7 . The semiconductor package of claim 6 , wherein the second reaction group chemically adsorbs the self-assembled monolayer to a surface of the mold layer.
8 . The semiconductor package of claim 6 , wherein the protection layer further includes an organic dielectric layer between the self-assembled monolayer and the mold layer.
9 . The semiconductor package of claim 1 , wherein the protection layer includes an inorganic dielectric material.
10 . A semiconductor package, comprising:
a lower semiconductor chip;
a plurality of semiconductor chips in a stack on the lower semiconductor chip in a first direction perpendicular to a top surface of the lower semiconductor chip;
a plurality of connection bumps between the lower semiconductor chip and a bottommost one of the plurality of semiconductor chips, and the plurality of connection bumps being between the plurality of semiconductor chips;
a protection layer that covers a lateral surface of each of the plurality of connection bumps;
a mold layer that covers lateral surfaces of the plurality of semiconductor chips and extends between the bottommost one of the plurality of semiconductor chips and the lower semiconductor chip, and the mold layer extends between the plurality of semiconductor chips; and
the mold layer including at least one void within the mold layer and between the bottommost one of the plurality of semiconductor chips and the lower semiconductor chip or between the plurality of semiconductor chips,
wherein the at least one void exposes at least a portion of the protection layer.
11 . The semiconductor package of claim 10 , wherein
the plurality of connection bumps include a pair of connection bumps that are spaced apart from each other across the at least one void, and
the protection layer is between the at least one void and each of the pair of connection bumps.
12 . The semiconductor package of claim 10 , wherein
each of the plurality of semiconductor chips has a top surface and a bottom surface that are opposite to each other in the first direction,
each of the plurality of connection bumps includes a conductive pillar, a solder bump, and a conductive pad that are sequentially stacked on the bottom surface of each of the plurality of semiconductor chips, and
the protection layer covers a lateral surface of the solder bump and extends onto a lateral surface of the conductive pillar and a lateral surface of the conductive pad.
13 . The semiconductor package of claim 12 , wherein
the conductive pillar is adjacent to the bottom surface of each of the plurality of semiconductor chips,
the conductive pad is adjacent to the top surface of the lower semiconductor chip or the top surface of a corresponding one of the plurality of semiconductor chips, and
the solder bump is between the conductive pillar and the conductive pad.
14 . The semiconductor package of claim 10 , wherein
each of the plurality of semiconductor chips has a top surface and a bottom surface that are opposite to each other in the first direction, and
the protection layer extends between the mold layer and the bottom surface of each of the plurality of semiconductor chips, and the protection layer extends between the mold layer and the top surface of each of the plurality of semiconductor chips.