Cryptographic system for post-quantum cryptographic operations
Certain examples described herein relate to at least a cryptographic system and a method of operating a cryptographic system. The cryptographic system may be implemented as a co-processor for performing post-quantum cryptographic functions. The cryptographic system has a set of bus interfaces for coupling to an external computing system, a cryptographic math unit and a control unit. The cryptographic math unit in certain examples is adapted to provide one or more masked modes of operation that secure the cryptographic operations against side-channel and non-invasive attacks. The method of operating a cryptographic system involves annotating secret data and tracking those annotations through one or more arithmetic operations.
1 . A cryptographic system to perform post-quantum cryptographic operations for a communicatively-coupled computing system, the cryptographic system being separate from the communicatively-coupled computing system and comprising:
a set of bus interfaces for communicatively coupling the cryptographic system to one or more system buses of the computing system;
a cryptographic math unit; and
a control unit comprising at least one processor and memory to control the cryptographic math unit, wherein the control unit is communicatively coupled to the set of bus interfaces via a first internal bus and is communicatively coupled to the cryptographic math unit via a second internal bus, wherein the first and second internal buses do not allow access to internal cryptographic data of the cryptographic math unit during the cryptographic operations,
wherein the cryptographic math unit comprises:
a matrix memory to store a multi-dimensional array of data;
an address generator configured to receive control signals from the control unit and to control access to data within the matrix memory;
an arithmetic unit to perform a set of defined arithmetic operations upon data within the matrix memory as accessed using the address generator; and
a permutation unit configured to generate a random bit sequence, wherein the permutation unit is controlled by the control unit and is communicatively coupled to the arithmetic unit,
wherein the cryptographic system is configured to perform masked arithmetic computations by decomposing secret data values into a plurality of data shares, the control unit being configured to control the arithmetic unit and the address generator to apply at least one of the set of defined arithmetic operations as a plurality of independent linear operations on the respective plurality of data shares.
2 . The cryptographic system of claim 1 , wherein the cryptographic system comprises a masked mode of operation and, for the masked mode of operation, is configured to:
receive, via the set of bus interfaces, an instruction from the communicatively-coupled computing system to perform a masked arithmetic computation as a single atomic operation;
determine, at the control unit, a first set of control signals to control access to data within the matrix memory and a second set of control signals to control at least one operation of the arithmetic unit to perform the masked arithmetic computation;
decompose secret data values stored within the matrix memory into a plurality of masked data shares by applying one or more random bit sequences from the permutation unit to the secret data values; and
repeatedly apply the at least one operation on each of the plurality of data shares using the arithmetic unit to perform the masked arithmetic computation, the at least one operation being applied as a plurality of independent linear operations.
3 . The cryptographic system of claim 2 , wherein the cryptographic system is configured to, for the masked mode of operation:
retrieve an encrypted secret data value via the set of bus interfaces; and
decrypt the encrypted secret data value and store the decrypted data value in the matrix memory for decomposition into the masked data shares,
wherein a result of the at least one operation is only exported to the communicatively-coupled computing system in an encrypted form.
4 . The cryptographic system of claim 1 , wherein the permutation unit performs an ASCON permutation.
5 . The cryptographic system of claim 1 , wherein the control unit comprises a set of condition-free instructions that are stored in the memory and executed by the processor.
6 . The cryptographic system of claim 1 , wherein the permutation unit comprises:
an Extendable-Output Function-XOF-unit to apply cryptographic operations to generate an indefinite-length output stream,
wherein the XOF unit is controlled by the control unit and is communicatively coupled to the arithmetic unit.
7 . The cryptographic system of claim 6 , wherein the XOF unit is configured to perform one or more of: a cryptographic absorb operation, a cryptographic squeeze operation, a cryptographic sampling operation and a cryptographic random masking operation.
8 . The cryptographic system of claim 6 , wherein the XOF unit comprises a n-bit cryptographic state that is separated into a plurality of data shares for masked arithmetic computations.
9 . The cryptographic system of claim 6 , wherein the cryptographic system is configured to compute one or more of Winternitz hash chains and Merkle tree data.
10 . The cryptographic system of claim 1 , wherein the cryptographic system is configured to compute hash-based signatures by iteratively hashing data stored in the matrix memory.
11 . The cryptographic system of claim 1 , wherein the cryptographic system is configured to perform one or more of:
key establishment functions including one or more of encryption and decryption;
digital signature functions including one or more of digital signature generation and digital signature verification; and
stateful hash-based signatures.
12 . The cryptographic system of claim 11 , wherein the cryptographic system is configured to:
implement one or more of: lattice post-quantum key establishment functions and code-based post-quantum key establishment functions;
implement one or more of: lattice post-quantum digital signature functions, code-based post-quantum digital signature functions, hash-based post-quantum digital signature functions, and multivariate post-quantum digital signature functions; and
implement hierarchical signature system functions.
13 . The cryptographic system of claim 1 , wherein the arithmetic unit comprises an arithmetic pipeline unit that receives control data indicating a selected operation to perform from the control unit and that performs the selected operation as a plurality of stages over time.
14 . The cryptographic system of claim 13 , wherein the plurality of stages comprise a plurality of parallel processing streams, the plurality of parallel processing streams receiving data accessed from the matrix memory.
15 . The cryptographic system of claim 1 , wherein the processor of the control unit is configured to receive vector instructions via the set of bus interfaces and convert the vector instructions into control instructions for vector operations for the cryptographic math unit.
16 . The cryptographic system of claim 1 , wherein the set of bus interfaces comprise:
a set of control registers writable by at least one processor of the communicatively-coupled computing system; and
a set of cryptographic registers for secret cryptographic data.
17 . The cryptographic system of claim 1 , wherein the control unit is configured to convert from a first masking format to a second masking format.
18 . The cryptographic system of claim 1 , wherein the control unit is configured to implement one or more of Boolean masking and arithmetic masking.
19 . A method of operating a cryptographic system, the cryptographic system being separate from a communicatively-coupled computing system, the method comprising:
receiving, via a set of bus interfaces of the cryptographic system, an instruction from the communicatively-coupled computing system to perform a masked arithmetic computation as a single atomic operation;
accessing, by a control unit of the cryptographic system comprising at least one processor and memory, the instruction as written to the set of bus interfaces;
determining, at the control unit, a first set of control signals to control access to data within a matrix memory of the cryptographic system and a second set of control signals to control at least one operation of an arithmetic unit of the cryptographic system to perform the masked arithmetic computation;
decomposing secret data values stored within the matrix memory into a plurality of masked data shares by applying one or more random bit sequences from a permutation unit of the cryptographic system to the secret data values; and
repeatedly applying, using the first and second set of control signals, the at least one operation on each of the plurality of data shares using the arithmetic unit to perform the masked arithmetic computation, the at least one operation being applied as a plurality of independent linear operations,
wherein during at least said decomposing and said repeatedly applying, the control unit is prevented from accessing the contents of the matrix memory or arithmetic unit.
20 . The method of claim 19 , comprising:
exporting a non-secret result of the masked arithmetic computation to the communicatively-coupled computing system via the set of bus interfaces of the cryptographic system,
including, in a case where the masked arithmetic computation provides a secret result, encrypting the secret result prior to exporting.
21 . The method of claim 19 , comprising:
retrieving an encrypted secret data value via the set of bus interfaces; and
decrypting the encrypted secret data value within the cryptographic system; and
storing the decrypted data value in the matrix memory for decomposition into the masked data shares.