Phase-change memory structure and phase-change memory device including the same
A phase-change memory structure includes lower and upper electrodes spaced apart from each other, and a phase-change material stack between the lower and upper electrodes. The phase-change material stack includes a plurality of phase-change layers, at least two phase-change layers of the plurality of phase-change layers have different phase-change temperatures, and a plurality of barrier layers between the plurality of phase-change layers The at least two phase-change layers of the plurality of phase-change layers have different thicknesses.
1 . A phase-change memory structure, comprising:
a lower electrode and an upper electrode, the lower electrode and the upper electrode spaced apart from each other; and
a phase-change material stack between the lower electrode and the upper electrode, the phase-change material stack including a plurality of phase-change layers, at least two phase-change layers of the plurality of phase-change layers having different phase-change temperatures, and a plurality of barrier layers between the plurality of phase-change layers,
wherein the at least two phase-change layers of the plurality of phase-change layers have different thicknesses.
2 . The phase-change memory structure of claim 1 , wherein a contact area between the lower electrode and the phase-change material stack is identical in size to a contact area between the upper electrode and the phase-change material stack.
3 . The phase-change memory structure of claim 1 , wherein at least one of the plurality of phase-change layers has a thickness of about 0.01 nm to about 10 nm.
4 . The phase-change memory structure of claim 1 , wherein each phase-change layer of the plurality of phase-change layers comprises a multi-component chalcogenide material having a crystallization temperature of about 100 degrees Celsius to about 3000 degrees Celsius.
5 . The phase-change memory structure of claim 1 , wherein each barrier layer of the plurality of barrier layers comprises a non-oxide material having a thermal conductivity of about 0.001 W/mK to about 1 W/mK.
6 . The phase-change memory structure of claim 1 , wherein the plurality of phase-change layers are vertically symmetrical with respect to a central portion of the phase-change material stack.
7 . The phase-change memory structure of claim 6 , wherein respective phase-change temperatures of the plurality of phase-change layers are proportional to respective distances of the plurality of phase-change layers from the central portion of the phase-change material stack.
8 . The phase-change memory structure of claim 7 , wherein
the respective phase-change temperatures of the plurality of phase-change layers are respective crystallization temperatures of the plurality of phase-change layers, and
respective thicknesses of the plurality of phase-change layers are inversely proportional to the respective distances of the plurality of phase-change layers from the central portion of the phase-change material stack.
9 . The phase-change memory structure of claim 8 , wherein a thermal conductivity of each phase-change layer of the plurality of phase-change layers is equal to or greater than a thermal conductivity of each barrier layer of the plurality of barrier layers.
10 . The phase-change memory structure of claim 8 , wherein the phase-change memory structure is configured to implement a multi-bit operation based on crystallization of each phase-change layer of the plurality of phase-change layers.
11 . The phase-change memory structure of claim 7 , wherein
the respective phase-change temperatures of the plurality of phase-change layers are respective melting temperatures of the plurality of phase-change layers, and
respective thicknesses of the plurality of phase-change layers are proportional to the respective distances of the plurality of phase-change layers from the central portion of the phase-change material stack.
12 . The phase-change memory structure of claim 11 , wherein a thermal conductivity of each phase-change layer of the plurality of phase-change layers is greater than or equal to a thermal conductivity of each barrier layer of the plurality of barrier layers.
13 . The phase-change memory structure of claim 11 , wherein the phase-change memory structure is configured to implement a multi-bit operation based on amorphization of each phase-change layer of the plurality of phase-change layers.
14 . A phase-change memory device, comprising:
a plurality of memory cells,
wherein each memory cell of the plurality of memory cells includes a phase-change memory structure and a selector, the phase-change memory structure and the selector connected in series to each other,
wherein the phase-change memory structure includes
a lower electrode and an upper electrode, the lower electrode and the upper electrode spaced apart from each other, and
a phase-change material stack between the lower electrode and the upper electrode, the phase-change material stack including a plurality of phase-change layers, at least two phase-change layers of the plurality of phase-change layers having different phase-change temperatures, and a plurality of barrier layers between the plurality of phase-change layers, and
wherein the at least two phase-change layers of the plurality of phase-change layers have different thicknesses.
15 . The phase-change memory device of claim 14 , wherein the phase-change memory device has a three-dimensional cross-point structure.
16 . The phase-change memory device of claim 14 , wherein a contact area between the lower electrode and the phase-change material stack is identical in size to a contact area between the upper electrode and the phase-change material stack, and at least one of the plurality of phase-change layers has a thickness of 10 nm or less.
17 . The phase-change memory device of claim 14 , wherein
the plurality of phase-change layers are vertically symmetrical with respect to a central portion of the phase-change material stack, and
respective phase-change temperatures of the plurality of phase-change layers are proportional to respective distances of the plurality of phase-change layers from the central portion of the phase-change material stack.
18 . The phase-change memory device of claim 17 , wherein
the respective phase-change temperatures of the plurality of phase-change layers are crystallization temperatures of the plurality of phase-change layers, and
respective thicknesses of the plurality of phase-change layers are inversely proportional to the respective distances of the plurality of phase-change layers from the central portion of the phase-change material stack.
19 . The phase-change memory device of claim 17 , wherein
the respective phase-change temperatures of the plurality of phase-change layers are melting temperatures of the plurality of phase-change layers, and
respective thicknesses of the plurality of phase-change layers are proportional to the respective distances of the plurality of phase-change layers from the central portion of the phase-change material stack.
20 . An electronic device comprising the phase-change memory device of claim 14 .