In-situ low temperature dielectric deposition and selective trim of phase change materials
A method of fabricating a resistive semiconductor memory structure that provides in-situ selective etch of phase change materials during deposition of dielectric at low temperature (in the same chamber). The method provides, to a single processing chamber, a semiconductor wafer including a trimmed resistive memory device structure having one or more layers of phase change material used to form a resistive memory device. The one or more layers of phase change material have oxidized sidewall surfaces as a result of a prior etching step where a whole stack structure of the layers forming the resistive memory structure is etched. Then, an encapsulating of the trimmed resistive memory device structure is performed by depositing, within the processing chamber, using a PECVD, a layer of dielectric material, and during the encapsulating, etching, within the processing chamber, the wafer to selectively remove the phase change material oxidation at the sidewall surfaces.
1 . A method of fabricating a resistive memory semiconductor device comprising:
providing, within a processing chamber, a semiconductor wafer including a trimmed resistive memory device structure having one or more layers of phase change material used to form the resistive memory device, said one or more layers of phase change material having oxidized sidewall surfaces; and
encapsulating said trimmed resistive memory device structure by depositing, within the processing chamber, a layer of dielectric material, and during said encapsulating, simultaneously etching, within the processing chamber, said wafer to selectively remove the oxidized sidewall surfaces of all the one or more layers of said phase change material, wherein said depositing comprises using a plasma enhanced deposition process; and
during said simultaneously etching and depositing: tuning processing parameters for generating a plasma used to selectively etch said oxidized sidewall surfaces of all the one or more layers of said phase change material and for controlling said depositing a layer of dielectric material.
2 . The method of claim 1 , wherein said etching to selectively remove said oxidized sidewall surfaces of said phase change material results in a reduced critical dimension thickness of each said one or more layers of phase change material.
3 . The method of claim 1 , wherein said depositing of encapsulating dielectric material is performed in said processing chamber under a low temperature condition.
4 . The method of claim 1 , wherein said processing chamber is an air-free environment.
5 . The method of claim 1 , wherein each said one or more phase change material layers is a chalcogenide-based material having a composition maintained after said etching.
6 . A stacked semiconductor resistive memory device structure comprising:
a bottom electrode;
an organic material layer formed above said bottom electrode;
a switching material layer formed above said organic material layer, wherein said switching material layer includes undercut portions beneath said first intermediate barrier layer and undercut portions above said organic material layer formed above said bottom electrode;
a first intermediate barrier layer formed above said switching material layer, said first intermediate barrier layer comprising:
a first organic material layer located above said switching material layer and a first metal-containing material layer above said first organic material layer;
a phase change material layer formed above said first intermediate barrier layer;
a second intermediate barrier layer formed above said phase change material layer, said phase change material layer including undercut portions beneath said second intermediate barrier layer and undercut portions above said first intermediate barrier layer, said second intermediate barrier layer comprising:
a second metal-containing material layer disposed above said phase change material layer and a second organic material layer disposed above said second metal-containing material layer;
a top electrode formed above said second intermediate barrier layer, wherein a width of said switching material layer and a width of said phase change material layer is reduced relative to a width of each said first intermediate barrier layer and a width of said second intermediate barrier layer,
a dielectric material layer of a single, uniform composition encapsulating said top electrode, said second intermediate barrier layer, said phase change material layer, said first intermediate barrier layer, said switching material layer and said organic material layer,
wherein both said switching material layer and said phase change material layer includes sidewalls, said switching material layer and said phase change material layer sidewalls comprising thicker encapsulation dielectric material layer portions than the remaining portions of said dielectric material layer of said single, uniform composition encapsulating top electrode, said second intermediate barrier layer, said first intermediate barrier layer, and said organic material layer.
7 . The stacked semiconductor resistive memory device of claim 6 wherein said phase change material is a chalcogenide-based material composition.
8 . The stacked semiconductor resistive memory device of claim 6 , wherein said switching material layer is an ovonic threshold switch.
9 . A semiconductor memory device comprising:
a bottom electrode;
an organic material layer formed above said bottom electrode;
a phase change memory (PCM) cell;
an access device for enabling read or write access to said PCM cell, said access device formed above said organic material layer, wherein a width of said PCM cell and a width of said access device is reduced relative to a width of said organic material layer; and
a barrier layer disposed between said PCM cell and access device, wherein said barrier layer disposed between said PCM cell and access device comprises:
a first organic material layer located above said access device and a first metal-containing material layer above said first organic material layer; and
a further barrier layer formed above said PCM cell; and
a top electrode formed above said further barrier layer, said further barrier layer disposed between said PCM cell and said top electrode comprising:
a second metal-containing material layer disposed above said PCM cell and a second organic material layer disposed above said second metal-containing material layer, wherein a width of said PCM cell and a width of said access device is reduced relative to a width of said barrier layer and a width of said further barrier layer; and
a dielectric material layer of a single, uniform composition encapsulating said top electrode, said further barrier layer, said PCM cell, said barrier layer, said access device and said organic material layer,
wherein both said access device and said PCM cell includes sidewalls, wherein said access device and said PCM cell sidewalls comprise thicker encapsulation dielectric material layer portions than the remaining portions of said dielectric material layer of said single, uniform composition encapsulating said top electrode, said barrier layer, said further barrier layer and said organic material layer.