Systems and techniques for forming silicon-on-oxide-on-silicon structures
Some embodiments of the present technology simplify the process of producing SOI wafers significantly compared to traditional methods. Furthermore, various embodiments provide a route for the integration of perovskite transition metal oxide thin films with different properties into SOI wafers. As such films display a wide array of novel electronic, magnetic, and optical phenomena, their integration into technologically-relevant SOI wafers will likely allow for the construction of a wide array of novel devices.
1 . A silicon-on-insulator-on-silicon platform comprising:
a silicon substrate;
a buffer layer of strontium titanate (SrTiO 3 ) or calcium titanate (CaTiO 3 ) epitaxially grown on the silicon substrate;
a functional oxide layer formed directly on the buffer layer and underlying a scavenging barrier insulating (SBI) oxide layer;
the SBIoxide layer formed on top of the functional oxide layer; and
a device silicon layer grown via direct epitaxial deposition on the SBI oxide layer, wherein:
the SBIoxide layer comprises:
a formation energy that is greater than a formation energy of silicon dioxide (SiO2) per oxygen atom; and
a phase that allows for lattice matching with the silicon present in the device silicon layer, wherein the lattice matching comprises less than 5% lattice mismatches between the SBI oxide layer and the silicon; and
wherein the SBI oxide layer and the functional oxide layer do not react with either the buffer layer or the device silicon layer.
2 . The silicon-on-insulator-on-silicon platform of claim 1 , further comprising an alternating arrangement of depositions of the functional oxide layer and the device silicon layer.
3 . The silicon-on-insulator-on-silicon platform of claim 2 , wherein the alternating arrangement of depositions of the functional oxide layer and the device silicon layer create a three-dimensional silicon-oxide-silicon integrated circuit.
4 . The silicon-on-insulator-on-silicon platform of claim 3 , wherein the integrated circuit includes an integrated photonic circuit, an integrated electronic circuit, an integrated optoelectronic circuit, or an integrated magneto-optic circuit.
5 . The silicon-on-insulator-on-silicon platform of claim 1 , wherein the functional oxide layer is ferroelectric or ferromagnetic.
6 . The silicon-on-insulator-on-silicon platform of claim 1 , wherein the functional oxide layer comprises BaTiO 3 or La x Sr 1-x MnO 3 .
7 . The silicon-on-insulator-on-silicon platform of claim 1 , wherein the SBI oxide layer comprises LaAlO 3 (LAO).
8 . The silicon-on-insulator-on-silicon platform of claim 1 , wherein the silicon substrate is a bulk silicon wafer or a silicon layer on a silicon-on-insulator wafer.
9 . A method for producing silicon-on-insulator-on-silicon platforms via direct deposition techniques, the method comprising:
creating a buffer layer by epitaxially growing a seed layer of strontium titanate (SrTiO 3 ) or calcium titanate (CaTiO 3 ) on a silicon substrate;
creating a scavenging barrier insulating (SBI) oxide layer on top of the buffer layer; and
applying, via direct epitaxial deposition, a top silicon layer on the SBI oxide layer, wherein the SBI oxide layer comprises:
a formation energy that is greater than a formation energy of silicon dioxide (SiO2) per oxygen atom; and
a phase that allows for lattice matching with the silicon present in the top silicon layer, wherein the lattice matching comprises less than 5% lattice mismatches between the SBI oxide layer and the silicon.
10 . The method of claim 9 , wherein applying the top silicon layer on the SBI oxide layer comprises using a two-step growth process with an initial Si layer deposited at a first temperature that is higher than a second temperature used during deposition of a second layer.
11 . The method of claim 9 , further comprising smoothing a surface of the top silicon layer using chemical-mechanical planarization.
12 . The method of claim 9 , further comprising applying alternating depositions of functional oxides and crystalline silicon.
13 . The method of claim 12 , wherein the alternating depositions of the functional oxides and crystalline silicon create a three-dimensional silicon-oxide-silicon integrated circuit.
14 . The method of claim 13 , wherein the three-dimensional silicon-oxide-silicon integrated circuit includes an integrated photonic circuit, an integrated electronic circuit, an integrated optoelectronic circuit, or an integrated magneto-optic circuit.
15 . The method of claim 9 , wherein the SBI oxide layer comprises LaAlO 3 .
16 . The method of claim 9 , wherein creating the SBI oxide layer on top of the buffer layer comprises growing an epitaxial layer of the SBI oxide layer on top of the buffer layer.
17 . The method of claim 9 , wherein the SBI oxide layer comprises LAO and the method further comprises:
growing an amorphous 1 nm LAO at a first temperature and oxygen pressure; annealing to crystallize; and
continuing normal LAO deposition.
18 . The method of claim 9 , wherein the SBI oxide layer comprises LAO and the SBI oxide layer is grown while temperature and oxygen pressure are increasing to LAO growth conditions.
19 . The method of claim 9 , further comprising use of a co-deposition of La/Al or alternating layers of LaO and AlO2 to control surface termination.
20 . The method of claim 9 , wherein the SBI oxide layer comprises LAO and the method further comprises selecting a surface composition of LAO to control wetting.
21 . The method of claim 9 , wherein the silicon substrate is a bulk silicon wafer or a silicon layer from a silicon-on-insulator wafer.
22 . A method for integrating crystalline silicon atop functional oxides via an epitaxial, insulating scavenging barrier (SBI) oxide layer, the method comprising:
creating a buffer layer by epitaxially growing a seed layer of strontium titanate (SrTiO 3 ) or calcium titanate (CaTiO 3 ) on a silicon substrate;
creating a functional oxide layer directly on the buffer layer and underlying a scavenging barrier insulating (SBI) oxide layer;
creating the SBI oxide layer on top of the functional oxide layer; and
applying, via direct epitaxial deposition, a top silicon layer on the SBI oxide layer,
wherein the SBI oxide layer comprises:
a formation energy that is greater than a formation energy of silicon dioxide (SiO2) per oxygen atom; and
a phase that allows for lattice matching with the silicon present in the top silicon layer, wherein the lattice matching comprises less than 5% lattice mismatches between the SBI oxide layer and the silicon layer.
23 . The method of claim 22 , wherein the SBI oxide-layer comprises □-alumina or LaAlO 3 .
24 . The method of claim 22 , wherein the functional oxide layer comprises BaTiO 3 or LaSrMnO 3 .
25 . The method of claim 22 , wherein the silicon substrate is a bulk silicon wafer or a silicon layer on a silicon-on-insulator wafer.
26 . The method of claim 22 , wherein the functional oxide layer is ferroelectric, ferromagnetic, elastooptic, magnetoelastic, or piezoelectric.
27 . The method of claim 22 , wherein the functional oxide layer comprises BaTiO 3 , La x Sr 1-x MnO 3 , or SrMnO 3 .
28 . A silicon-on-insulator-on-silicon platform comprising:
a silicon substrate;
a buffer layer comprising an epitaxial oxide buffer layer epitaxially grown on the silicon substrate;
an insulating oxide layer formed on top of the buffer layer, wherein the insulating oxide layer is a scavenging barrier layer to prevent oxygen scavenging from the buffer layer; and
a device silicon layer grown via direct epitaxial deposition on the insulating oxide layer, wherein the insulating oxide layer comprises:
a formation energy that is greater than a formation energy of silicon dioxide (SiO2) per oxygen atom; and
a phase that allows for lattice matching with the silicon present in the device silicon layer, wherein the lattice matching comprises less than 5% lattice mismatches between the insulating oxide layer and the silicon.
29 . The silicon-on-insulator-on-silicon platform of claim 28 , wherein the epitaxial oxide buffer layer comprises strontium titanate (SrTiO 3 ) or calcium titanate (CaTiO 3 ).
30 . The silicon-on-insulator-on-silicon platform of claim 28 , wherein the silicon substrate is a bulk silicon wafer or a silicon layer on a silicon-on-insulator wafer.