Duplicating memory content with chipset attached memory
Duplicating memory content with chipset attached memory is described. In accordance with the described techniques, contents of a system memory are duplicated on a chipset attached memory over a chipset link. Memory requests are serviced using the contents of the system memory and the contents on the chipset attached memory. Servicing the memory requests includes servicing a first portion of a read request using the contents of the system memory and a second, remaining portion of the read request using the contents on the chipset attached memory. Servicing the memory requests further includes communicating a write request to the system memory and to the chipset attached memory.
1 . An apparatus comprising:
a system memory attached to a first memory controller;
a chipset attached memory connected to the system memory via a southbridge; and
a second memory controller attached to the chipset attached memory to:
obtain contents of the system memory;
duplicate the contents of the system memory on the chipset attached memory over a chipset link; and
service memory requests using the contents of the system memory and the contents on the chipset attached memory in parallel.
2 . The apparatus of claim 1 , wherein to service the memory requests using the contents of the system memory and the contents on the chipset attached memory, the second memory controller is further configured to:
service a first portion of a read request using the contents of the system memory; and
service a second, remaining portion of the read request using the contents of the chipset attached memory.
3 . The apparatus of claim 1 , wherein to service the memory requests using the contents of the system memory and the contents on the chipset attached memory, the second memory controller is further configured to communicate a write request to the system memory and to the chipset attached memory.
4 . The apparatus of claim 1 , wherein the second memory controller duplicates the contents of the system memory on the chipset attached memory over the chipset link in response to receiving a request for a mirrored memory configuration.
5 . The apparatus of claim 1 , wherein the second memory controller is further configured to dynamically allocate and deallocate portions of the system memory and the chipset attached memory for storing the contents.
6 . The apparatus of claim 5 , wherein the second memory controller is configured to dynamically allocate and deallocate the portions of the system memory and the chipset attached memory for storing the contents in response to receiving an indication of at least one of a physical adjustment to the system memory or the chipset attached memory, a retraining of the system memory or the chipset attached memory, and a resetting of the system memory or the chipset attached memory.
7 . The apparatus of claim 1 , further comprising a processing unit, and wherein the memory requests are received by the second memory controller from one or more applications executing on the processing unit.
8 . The apparatus of claim 7 , wherein the processing unit is configured to execute one or more tasks of an operating system or the one or more applications using the contents on the chipset attached memory while the system memory is unavailable.
9 . The apparatus of claim 1 , wherein the second memory controller is further configured to identify corrupted data in the system memory based on discrepancies between a first read data stream from a memory section of the system memory and a second read data stream from a corresponding memory section of the chipset attached memory.
10 . The apparatus of claim 9 , wherein the second memory controller is further configured to correct the corrupted data by writing data from the corresponding memory section of the chipset attached memory to the memory section of the system memory.
11 . The apparatus of claim 1 , wherein the system memory comprises a type of random-access memory (RAM).
12 . The apparatus of claim 1 , wherein the chipset attached memory comprises dynamic random-access memory (DRAM) or non-volatile random-access memory (NVRAM).
13 . A method comprising:
obtaining contents of a system memory attached to a first memory controller;
writing duplicate contents of the system memory to a chipset attached memory that is attached to a second memory controller and is connected to the system memory via a southbridge;
servicing read requests, received from one or more applications, using the contents of the system memory and the duplicate contents of the chipset attached memory in parallel; and
storing write requests to the contents of the system memory and to the duplicate contents of the chipset attached memory.
14 . The method of claim 13 , wherein the writing the duplicate contents of the system memory to the chipset attached memory is performed over a chipset link in response to a request for a mirrored memory configuration.
15 . The method of claim 13 , further comprising dynamically allocating and deallocating portions of the system memory and the chipset attached memory for storing the contents and the duplicate contents, respectively.
16 . The method of claim 13 , wherein the servicing the read requests, received from the one or more applications, using the contents of the system memory and the duplicate contents of the chipset attached memory in parallel comprises:
servicing a first portion of the read requests using the contents of the system memory; and
while servicing the first portion of the read requests using the contents of the system memory, servicing a second, remaining portion of the read requests using the duplicate contents of the chipset attached memory.
17 . The method of claim 13 , further comprising:
executing, via a processing unit, one or more tasks of an operating system or an application using the duplicate contents of the chipset attached memory in response to an indication that the system memory is unavailable.
18 . A system comprising:
a system memory attached to a first memory controller and configured to store contents;
a chipset attached memory attached to a second memory controller and connected to the system memory via a southbridge to store the contents of the system memory in a mirrored manner; and
a processing unit to:
execute one or more tasks of an operating system using the contents of the system memory in response to a first indication that the system memory is available for servicing memory requests; and
continue executing the one or more tasks using the contents of the chipset attached memory in response to a second indication that the system memory is not available for servicing the memory requests.
19 . The system of claim 18 , further comprising a chipset link, and wherein the chipset attached memory is separate from the system memory and communicates with the processing unit via the chipset link.
20 . The system of claim 18 , wherein the second memory controller is configured to:
in response to the first indication that the system memory is available for servicing the memory requests:
communicate a first portion of a read request to the system memory and a second portion of the read request to the chipset attached memory over a chipset link; and
communicate a write request to the system memory and to the chipset attached memory over the chipset link; and
in response to the second indication that the system memory is not available for servicing the memory requests:
communicate the first portion and the second portion of the read request to the chipset attached memory over the chipset link; and
communicate the write request to the chipset attached memory over the chipset link.