Machine-learning-based power/ground (P/G) via removal
A method, a system, and non-transitory computer readable medium for power and ground (P/G) routing for an integrated circuit (IC) design are provided. The method includes generating input features for a machine-learning (ML) model based on IR drop and routing congestion analysis for a P/G network for the IC design, and modifying a set of P/G vias or a set of P/G wires in the P/G network according to modifications identified by the ML model. The ML model comprises a feature extractor pre-trained using a plurality of images of P/G vias and P/G wires.
1 . A method for power and ground (P/G) routing for an integrated circuit (IC) design, the method comprising:
generating, using one or more processors, input features for a machine-learning (ML) model based on IR drop and routing congestion analysis for a P/G network for the IC design; and
modifying, using the one or more processors, one or more of a P/G via and a P/G wire in the P/G network according to modifications determined by the ML model, wherein the ML model comprises a feature extractor pre-trained using a plurality of images of P/G vias and P/G wires.
2 . The method of claim 1 , wherein performing the IR drop and the routing congestion analysis comprises:
partitioning the IC design into a plurality of routing grids;
determining a congestion score for a grid of the plurality of routing grids based on a demand and capacity associated with the grid; and
determining the congestion score of a target cell based on the score of the grid comprising the target cell and grids located within a bounding box associated with the target cell.
3 . The method of claim 1 , wherein generating the input features comprises: generating a density map for P/G vias or P/G wires of the P/G network for one or more metal layers of the IC design; and
normalizing the density map to obtain an image of a P/G via or a P/G wire.
4 . The method of claim 1 , wherein the ML model is a neural network.
5 . The method of claim 1 , wherein an objective of the ML model is to reduce an error between a measured IR drop and a predicted IR drop, and between a desired congestion score and a predicted congestion score, wherein the ML model is a multitask learning model and the ML model is trained using the plurality of images of P/G vias and P/G wires.
6 . The method of claim 1 , further comprising:
identifying a modification to a set of P/G vias or a set of P/G wires based on an IR drop distribution map generated using a k-means algorithm, wherein the IR drop distribution map is a function of a voltage drop and a position of a P/G via.
7 . The method of claim 6 , further comprising:
regenerating the input features based on the modification.
8 . The method of claim 1 , further comprising:
modifying another set of P/G vias or another set of P/G wires when a modification count is less than a threshold, wherein the threshold is indicative of a maximum number of P/G vias or P/G wires to be removed, a maximum number of time a modification of a P/G via or a P/G wire can be reserved, or a maximum number of times a modification of a P/G via or a P/G wire can be performed.
9 . The method of claim 1 , wherein modifying a set of P/G vias and a set of P/G wires comprises:
removing a P/G via or a P/G wire when an IR drop performance does not degrade by its removal.
10 . A system for power and ground (P/G) routing for an integrated circuit (IC), the system comprising:
a memory storing instructions; and
a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
generate input features for a machine-learning (ML) model based on IR drop and routing congestion analysis for a P/G network for the IC design, and
modify one or more of P/G via and P/G wire in the P/G network according to modifications determined by the ML model, wherein the ML model comprises a feature extractor pre-trained using a plurality of images of P/G vias and P/G wires.
11 . The system of claim 10 , wherein the processor is further configured to:
partition the IC design into a plurality of routing grids;
determine a congestion score for a grid of the plurality of routing grids based on a demand and capacity associated with the grid; and
determine the congestion score of a target cell based on the score of the grid comprising the target cell and grids located within a bounding box associated with the target cell.
12 . The system of claim 10 , wherein the processor is further configured to:
generate a density map for P/G vias or P/G wires of the P/G network for one or more metal layers of the IC design; and
normalize the density map to obtain an image of a P/G via or P/G wire.
13 . The system of claim 10 , wherein the ML model is a neural network.
14 . The system of claim 10 , wherein an objective of the ML model is to reduce an error between a measured IR drop and a predicted IR drop and between a desired congestion score and a predicted congestion score, wherein the ML model is a multitask learning model and the ML model is trained using the plurality of images of P/G vias and P/G wires.
15 . The system of claim 10 , wherein the processor is further configured to:
identify a modification to a set of P/G vias or a set of P/G wires based on a IR drop distribution map generated using a k-means algorithm, wherein the IR drop distribution map is a function of a voltage drop and a position of a P/G via.
16 . A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
acquire an integrated circuit (IC) design;
generate a P/G network for the IC design;
perform an IR drop and routing congestion analysis for the P/G network for the IC design; and
modify the P/G network according to modifications determined by a machine learning (ML) model based at least on the IR drop and routing congestion analysis, wherein an ML model objective is to decrease routing congestion with less IR drop overhead, and wherein the ML model comprises a feature extractor pre-trained using a plurality of images of P/G vias and P/G wires.
17 . The non-transitory computer readable medium of claim 16 , wherein the processor is further configured to:
partition the IC design into a plurality of routing grids;
determine a congestion score for a grid of the plurality of routing grids based on a demand and capacity associated with the grid; and
determine the congestion score of a target cell based on the score of the grid comprising the target cell and grids located within a bounding box associated with the target cell.
18 . The non-transitory computer readable medium of claim 16 , wherein the ML model is a neural network.
19 . The non-transitory computer readable medium of claim 16 , wherein the processor is further configured to:
generate input features for the ML model based on the IR drop and routing congestion analysis.
20 . The non-transitory computer readable medium of claim 16 , wherein the processor is further configured to:
generate a density map for P/G vias or PG wires for one or more metal layers of the IC design; and
normalize the density map to obtain a P/G via image or a P/G wire image.