Semiconductor device and method of manufacturing the same
A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device comprises a first electrical conductor, a second electrical conductor, a third electrical conductor, a plurality of metal features and a plurality of active regions. The first electrical conductor extends along a first direction and is electrically coupled to a first voltage. The second electrical conductor extends along the first direction and is electrically coupled to a second voltage. The second voltage is lower than the first voltage. The third electrical conductor extending along the first direction is electrically coupled to a third voltage and disposed between the first electrical conductor and the second electrical conductor. The metal features extend along a second direction perpendicular to the first direction and are formed above the first electrical conductor, the second electrical conductor and the third electrical conductor.
1 . A semiconductor device, comprising:
a first electrical conductor extending along a first direction and electrically coupled to a first voltage;
a second electrical conductor extending along the first direction and electrically coupled to a second voltage, wherein the second voltage is smaller than the first voltage;
a third electrical conductor extending along the first direction, electrically coupled to a third voltage and being disposed between the first electrical conductor and the second electrical conductor;
a plurality of metal features extending along a second direction perpendicular to the first direction and formed above the first electrical conductor, the second electrical conductor and the third electrical conductor; and
a plurality of active regions extending along the first direction and formed above the metal features.
2 . The semiconductor device of claim 1 , wherein a drain electrode of the semiconductor device is configured to receive the first voltage and the second voltage, and a source electrode of the semiconductor device is configured to receive the third voltage.
3 . The semiconductor device of claim 1 , wherein the metal features are electrically connected to the first electrical conductor, the second electrical conductor and the third electrical conductor through a plurality of vias.
4 . The semiconductor device of claim 1 , comprising:
a first cell, comprising the first electrical conductor; and
a second cell, comprising the second electrical conductor, wherein the third electrical conductor overlaps a first boundary between the first cell and the second cell.
5 . The semiconductor device of claim 4 , wherein the first electrical conductor overlaps a second boundary of the first cell parallel with the first boundary.
6 . The semiconductor device of claim 4 , wherein the second electrical conductor overlaps a third boundary of the second cell parallel with the first boundary.
7 . The semiconductor device of claim 1 , further comprising a doped region, wherein area of the doped region is larger than that of the first electrical conductor and overlapping the first electrical conductor.
8 . A semiconductor device comprising a plurality of cells, the semiconductor device comprising:
a first electrical conductor extending along a first direction and electrically coupled to a first voltage, wherein the first electrical conductor overlaps one of the boundaries between two adjacent ones of the cells;
a second electrical conductor extending along the first direction and electrically coupled to a third voltage, wherein the second electrical conductor overlaps another one of the boundaries between two adjacent ones of the cells;
a third electrical conductor extending along the first direction, electrically coupled to a second voltage and being disposed between the first electrical conductor and the second electrical conductor;
a metal feature extending along a second direction perpendicular to the first direction; and
an active region extending along the first direction and formed above the metal feature.
9 . The semiconductor device of claim 8 , wherein the third electrical conductor is spaced apart from the boundaries between two adjacent ones of the cells.
10 . The semiconductor device of claim 8 , wherein the first electrical conductor is coplanar with the second electrical conductor.
11 . The semiconductor device of claim 10 , wherein the first electrical conductor and the second electrical conductor are formed above the active region, and the third electrical conductor is formed below the active region.
12 . The semiconductor device of claim 10 , wherein the first electrical conductor and the second electrical conductor are formed below the active region, and the third electrical conductor is formed above the active region.
13 . The semiconductor device of claim 8 , wherein the first electrical conductor is spaced apart from the third electrical conductor by a first distance, wherein the active region has a width, and wherein the width is smaller than the first distance.
14 . The semiconductor device of claim 13 , wherein the first electrical conductor is spaced apart from the second electrical conductor by a second distance, and wherein the first distance is less than or equal to half of the second distance.
15 . The semiconductor device of claim 14 , wherein the second distance is substantially equal to twice the first distance and twice the width.
16 . The semiconductor device of claim 8 , wherein the third voltage applied to the second electrical conductor is different from the first voltage applied to the first electrical conductor.
17 . A method for manufacturing a semiconductor device, comprising:
forming a first electrical conductor extending along a first direction and electrically coupled to a first voltage;
forming a second electrical conductor extending along the first direction and electrically coupled to a second voltage, wherein the second voltage is smaller than the first voltage;
forming a third electrical conductor extending along the first direction, electrically coupled to a third voltage and being disposed between the first electrical conductor and the second electrical conductor;
forming a plurality of metal features extending along a second direction perpendicular to the first direction and formed above the first electrical conductor, the second electrical conductor and the third electrical conductor; and
forming a plurality of active regions extending along the first direction and formed above the metal features.
18 . The method of claim 17 , further comprising:
forming a first cell comprising the first electrical conductor; and
forming a second cell comprising the second electrical conductor, wherein the third electrical conductor overlaps a first boundary between the first cell and the second cell.
19 . The method of claim 18 , wherein the first electrical conductor overlaps a second boundary of the first cell parallel with the first boundary.
20 . The method of claim 17 , wherein the first voltage and the second voltage are electrically connected to a drain electrode, and the third voltage comprises a source electrode.