Gate-all-around structure with self substrate isolation and methods of forming the same
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a fin substrate having a first dopant concentration; an anti-punch through (APT) layer disposed over the fin substrate, wherein the APT layer has a second dopant concentration that is greater than the first dopant concentration; a nanostructure including semiconductor layers disposed over the APT layer; a gate structure disposed over the nanostructure and wrapping each of the semiconductor layers, wherein the gate structure includes a gate dielectric and a gate electrode; a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature disposed over the APT layer, wherein the gate structure is disposed between the first epitaxial S/D feature and the second epitaxial S/D feature; and an isolation layer disposed between the APT layer and the fin substrate, wherein a material of the isolation layer is the same as a material of the gate dielectric.
1 . A semiconductor device, comprising:
a substrate;
a base fin disposed over the substrate;
an isolation structure disposed over the substrate and interfacing sidewalls of the base fin;
an isolation layer disposed over the base fin;
a doped semiconductor layer over the isolation layer;
a first source/drain feature and a second source/drain feature disposed over the doped semiconductor layer;
a plurality of nanostructures disposed over the doped semiconductor layer and extending between the first source/drain feature and the second source/drain feature; and
a gate structure wrapping around each of the plurality of nanostructures and disposed over the doped semiconductor layer.
2 . The semiconductor device of claim 1 , wherein the doped semiconductor layer and the isolation layer extend without interruption under the first source feature, the gate structure, and the second source/drain feature.
3 . The semiconductor device of claim 1 , wherein the isolation layer comprises:
a first interfacial dielectric layer over the base fin;
a high-k dielectric layer over the first interfacial dielectric layer; and
a second interfacial dielectric layer over the high-k dielectric layer.
4 . The semiconductor device of claim 3 ,
wherein the first interfacial dielectric layer and the second interfacial dielectric layer comprise silicon oxide, silicon oxynitride, or hafnium silicate,
wherein the high-k dielectric layer comprises the isolation layer comprises hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, or zirconium oxide.
5 . The semiconductor device of claim 1 ,
wherein the base fin and the doped semiconductor layer comprise a dopant,
wherein the base fin comprises a first dopant concentration,
wherein the doped semiconductor layer comprises a second dopant concentration greater than the first dopant concentration.
6 . The semiconductor device of claim 1 , wherein the first source/drain feature and the second source/drain feature directly contact the doped semiconductor layer.
7 . The semiconductor device of claim 1 , further comprising:
a plurality of inner spacer features interleaving the plurality of nanostructures,
wherein the gate structure is spaced apart from the first source/drain feature by the plurality of inner spacer features.
8 . The semiconductor device of claim 7 , wherein the plurality of inner spacer features comprise silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or combinations thereof.
9 . A semiconductor structure, comprising:
a base fin disposed in an isolation structure;
an isolation layer disposed over the base fin;
a doped semiconductor layer over the isolation layer;
a source/drain feature disposed over the doped semiconductor layer;
a plurality of nanostructures disposed over the doped semiconductor layer and extending horizontally from a sidewall of the source/drain feature;
a gate structure wrapping around each of the plurality of nanostructures; and
a gate spacer layer disposed over the isolation structure and extending continuously along sidewalls of the isolation layer, the doped semiconductor layer, and a portion of the source/drain feature.
10 . The semiconductor structure of claim 9 , wherein the isolation layer is sandwiched between a top surface of the base fin and the doped semiconductor layer.
11 . The semiconductor structure of claim 9 , wherein the doped semiconductor layer and the isolation layer extend without interruption under the source feature and the gate structure.
12 . The semiconductor structure of claim 9 , wherein the isolation layer comprises:
a first interfacial dielectric layer over the base fin;
a high-k dielectric layer over the first interfacial dielectric layer; and
a second interfacial dielectric layer over the high-k dielectric layer.
13 . The semiconductor structure of claim 12 ,
wherein the first interfacial dielectric layer and the second interfacial dielectric layer comprise silicon oxide, silicon oxynitride, or hafnium silicate,
wherein the high-k dielectric layer comprises the isolation layer comprises hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, or zirconium oxide.
14 . The semiconductor structure of claim 9 ,
wherein the base fin and the doped semiconductor layer comprise a dopant,
wherein the base fin comprises a first dopant concentration,
wherein the doped semiconductor layer comprises a second dopant concentration greater than the first dopant concentration.
15 . The semiconductor structure of claim 9 , wherein the gate spacer layer comprises silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or combinations thereof.
16 . A semiconductor structure, comprising:
a substrate;
a base fin over the substrate;
an isolation structure disposed over the substrate and interfacing sidewalls of the base fin;
an isolation layer disposed over the base fin;
a doped semiconductor layer over the isolation layer;
a first source/drain feature and a second source/drain feature disposed over the doped semiconductor layer;
a plurality of nanostructures disposed over the doped semiconductor layer and extending between the first source/drain feature and the second source/drain feature; and
a gate structure wrapping around each of the plurality of nanostructures and disposed over the doped semiconductor layer,
wherein a thickness of the isolation layer is smaller than a distance between two adjacent ones of plurality of the nanostructures.
17 . The semiconductor structure of claim 16 ,
wherein the base fin and the doped semiconductor layer comprise a dopant,
wherein the base fin comprises a first dopant concentration,
wherein the doped semiconductor layer comprises a second dopant concentration greater than the first dopant concentration.
18 . The semiconductor structure of claim 16 , wherein the isolation layer comprises:
a first interfacial dielectric layer over the base fin;
a high-k dielectric layer over the first interfacial dielectric layer; and
a second interfacial dielectric layer over the high-k dielectric layer.
19 . The semiconductor structure of claim 18 ,
wherein the first interfacial dielectric layer and the second interfacial dielectric layer comprise silicon oxide, silicon oxynitride, or hafnium silicate,
wherein the high-k dielectric layer comprises the isolation layer comprises hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, or zirconium oxide.
20 . The semiconductor structure of claim 16 , wherein the thickness of the isolation layer is between about 2 nm and about 10 nm.