Majorana-based qubits in 3D topological insulator flakes
Embodiments of the present disclosure includes qubit architectures and qubit elements of a quantum processor. A superconductor region overlaps a three-dimensional topological insulator layer. A vortex region extends through the superconductor region to the three-dimensional topological insulator layer. A peripheral portion of the vortex region is located on an edge of the superconductor region.
1 . A quantum processor, comprising:
a three-dimensional topological insulator layer;
a superconductor region disposed on the three-dimensional topological insulator layer; and
a vortex region extending through the superconductor region to the three-dimensional topological insulator layer and having a peripheral portion located on an edge of the superconductor region, wherein the vortex region includes a cavity extending through the superconductor region to a surface of the three-dimensional topological insulator layer.
2 . The quantum processor of claim 1 , further comprising:
a gate region adjacent to the peripheral portion at the edge, the gate region being selectively tunable to activate tunneling in the three-dimensional topological insulator layer.
3 . The quantum processor of claim 1 , wherein the superconductor region includes a thin wall at the peripheral portion, the thin wall facilitating transfer of a Marjorana zero mode from the vortex region to an exterior of the superconductor region.
4 . The quantum processor of claim 1 , further comprising:
an aperture in the superconductor region at the peripheral portion.
5 . The quantum processor of claim 1 , further comprising:
a magnetic insulator region disposed on the three-dimensional topological insulator layer and at least partially surrounding the superconductor region.
6 . The quantum processor of claim 5 , further comprising:
a quantum dot region that includes a first gate region that extends in a first direction on the magnetic insulator region; and
a second gate region disposed on the magnetic insulator region and positioned between the first gate region and the superconductor region, wherein the superconductor region extends in the first direction.
7 . The quantum processor of claim 5 , wherein the superconductor region is adjacent to the magnetic insulator region on the three- dimensional topological insulator.
8 . A qubit architecture, comprising:
a three-dimensional topological insulator layer;
a first superconductor region on the three-dimensional topological insulator layer;
a first plurality of vortex regions extending through the first superconductor region to the three-dimensional topological insulator layer; and
a first plurality of peripheral portions of the first plurality of vortex regions located at a first edge of the first superconductor region, wherein each of the first plurality of vortex regions include a cavity extending through the first superconductor region to a surface of the three-dimensional topological insulator layer.
9 . The qubit architecture of claim 8 , wherein one or more of the first plurality of peripheral portions include a thin wall that facilitates transfer of a Marjorana zero mode of a vortex region of the first plurality of vortex regions to an exterior of the first superconductor region.
10 . The qubit architecture of claim 8 , wherein one or more of the first plurality of peripheral portions include an aperture extending through the first edge of the first superconductor region.
11 . The qubit architecture of claim 8 , further comprising:
a plurality of gate regions positioned on the first edge of the first superconductor region and adjacent to the first plurality of peripheral portions.
12 . The qubit architecture of claim 8 , further comprising:
a second plurality of vortex regions extending through the first superconductor region to the three-dimensional topological insulator layer; and
a second plurality of peripheral portions of the second plurality of vortex regions located on a second edge of the first superconductor region.
13 . The qubit architecture of claim 8 , further comprising:
a magnetic insulator layer on the three-dimensional topological insulator layer;
a quantum dot region extending along and spaced apart from the first edge; and
a plurality of gate regions on the magnetic insulator layer, the plurality of gate regions positioned between the quantum dot region and the first plurality of peripheral portions.
14 . The qubit architecture of claim 8 , further comprising:
a second superconductor region on the three-dimensional topological insulator layer; and
a second plurality of vortex regions extending through the second superconductor region to the three-dimensional topological insulator layer; and
a second plurality of peripheral portions of the second plurality of vortex regions located on a second edge of the second superconductor region.
15 . The qubit architecture of claim 8 , further comprising:
a quantum dot region extending along and spaced apart from the first edge;
a Fu wire; and
a first set of gate regions positioned on a side of the first superconductor region and configured to selectively couple the Fu wire to a vortex region of the first plurality of vortex regions.
16 . The qubit architecture of claim 15 , wherein the Fu wire includes:
a second superconductor region disposed on the three-dimensional topological insulator;
a second plurality of vortex regions extending through the second super conductor region to the three-dimensional topological insulator layer; and
a second set of gate region positioned on a side of the second superconductor region and configured to selectively couple the Fu wire to the quantum dot region.
17 . A quantum processor, comprising:
a three-dimensional topological insulator layer;
a superconductor region disposed on the three-dimensional topological insulator layer; and
a vortex region extending through the superconductor region to the three-dimensional topological insulator layer and having a peripheral portion located on an edge of the superconductor region, wherein the vortex region includes a cavity extending through the superconductor region to a surface of the three-dimensional topological insulator layer, and wherein the cavity is fillable with a material having a different electromagnetic characteristic than a superconductor material of the superconductor region.
18 . The quantum processor of claim 17 , further comprising:
a gate region adjacent to the peripheral portion at the edge, the gate region being selectively tunable to activate tunneling in the three-dimensional topological insulator layer.
19 . The quantum processor of claim 17 , further comprising:
a magnetic insulator region disposed on the three-dimensional topological insulator layer and at least partially surrounding the superconductor region.
20 . The quantum processor of claim 19 , further comprising:
a quantum dot region that includes a first gate region that extends in a first direction on the magnetic insulator region; and
a second gate region disposed on the magnetic insulator region and positioned between the first gate region and the superconductor region, wherein the superconductor region extends in the first direction.