IP Library › Granted Patent US 12,482,727
Granted Patent B2
US 12,482,727 · App. 17/896,780 · Granted Nov 25, 2025

Semiconductor device manufacturing method and semiconductor device

Inventor: Yoshiaki Takahashi (Nagano, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L23/49513H01L21/56H01L23/293H01L23/3135H01L23/49822H01L24/29H01L24/83H01L24/45H01L24/48H01L24/73H01L2224/29109H01L2224/29111H01L2224/29113H01L2224/29117H01L2224/29118H01L2224/2912H01L2224/29138H01L2224/29139H01L2224/29147H01L2224/29155H01L2224/29157H01L2224/45124H01L2224/45147H01L2224/48225H01L2224/73265H01L2224/83801
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Quick Facts
Patent No.
US 12,482,727
App. No.
17/896,780
Granted
Nov 25, 2025
Kind
B2
Abstract

A semiconductor device manufacturing method includes preparing a semiconductor chip and a conductive plate having a front surface that includes a disposition area on which the semiconductor chip is to be disposed, forming a supporting portion in a periphery of the disposition area of the conductive plate such that the supporting portion protrudes from a bottom of the disposition area in an upward direction orthogonal to the front surface of the conductive plate, bonding the semiconductor chip to the disposition area via bonding material applied to the disposition area, coating the front surface of the conductive plate, including the semiconductor chip and the supporting portion, with a coating layer, and after the coating, sealing the front surface of the conductive plate, including the semiconductor chip and the supporting portion, with sealing material.

Claims (41)

1 . A semiconductor device manufacturing method, comprising:

preparing a semiconductor chip and a conductive plate having a front surface that includes a disposition area on which the semiconductor chip is to be disposed;

forming a supporting portion so as to surround an entire periphery of the disposition area of the conductive plate such that a highest point of the supporting portion is located at a level higher than a level of a bottom of the disposition area in an upward direction orthogonal to the front surface of the conductive plate;

bonding the semiconductor chip to the disposition area via bonding material applied to the disposition area;

entirely coating the front surface of the conductive plate, including the semiconductor chip and the supporting portion, with a coating layer; and

after the coating, sealing the front surface of the conductive plate, including the semiconductor chip and the supporting portion, with sealing material.

2 . The semiconductor device manufacturing method according to claim 1 , wherein

the preparing includes forming the conductive plate on a multi-layer board having a flat plate shape, in an area adjacent to a part of an outer periphery of the multi-layer board,

the disposition area is set on the conductive plate in an area adjacent to the part of the outer periphery of the multi-layer board, and

the supporting portion is provided in a portion of the periphery of the disposition area, the portion of the periphery of the disposition area facing the part of the outer periphery of the multi-layer board.

3 . The semiconductor device manufacturing method according to claim 1 , wherein the supporting portion is continuously formed to surround an entire disposition area.

4 . The semiconductor device manufacturing method according to claim 1 , wherein the coating is performed under coating pressure, and the sealing is performed under sealing pressure that is lower than the coating pressure.

5 . The semiconductor device manufacturing method according to claim 4 , wherein the coating pressure is in a range of 0.5×10 5 Pa to 1.5×10 5 Pa.

6 . The semiconductor device manufacturing method according to claim 4 , wherein the sealing pressure is a range of 1.0×10 3 Pa to 1.0×10 4 Pa.

7 . The semiconductor device manufacturing method according to claim 1 , wherein

the forming includes forming a concave portion in the disposition area such that a bottom of the concave portion has a level lower in the upward direction than is a level of the front surface of the conductive plate, and

the bonding includes applying the bonding material to the concave portion to bond the semiconductor chip to the concave portion via the bonding material.

8 . The semiconductor device manufacturing method according to claim 1 , wherein

the forming includes forming the supporting portion in the periphery of the disposition area such that the highest point of the supporting portion in the upward direction is located at a level higher than is a level of the front surface of the conductive plate, and

the bonding includes applying the bonding material to the disposition area to bond the semiconductor chip to the disposition area via the bonding material.

9 . The semiconductor device manufacturing method according to claim 8 , wherein the supporting portion is a wire extending in the periphery along the disposition area or is resist material applied to the periphery along the disposition area.

10 . The semiconductor device manufacturing method according to claim 1 , wherein a chip front surface of the semiconductor chip bonded by the bonding is located at a level higher than the highest point of the supporting portion in the upward direction.

11 . The semiconductor device manufacturing method according to claim 1 , wherein the coating layer is made of thermosetting resin as a main component thereof, and the thermosetting resin is polyamide resin, polyamide imide resin, or polyetherimide resin.

12 . The semiconductor device manufacturing method according to claim 1 , wherein a void is included between the bonding material and the coating layer.

13 . A semiconductor device, comprising:

a semiconductor chip;

a conductive plate having a front surface that includes a disposition area to which the semiconductor chip is bonded via a bonding material, the conductive plate including a supporting portion that surrounds an entire periphery of the disposition area, a highest point of the support portion being located at a level higher than a level of a bottom of the disposition area in an upward direction orthogonal to the front surface of the conductive plate;

a coating layer that entirely covers the front surface of the conductive plate, including the semiconductor chip and the supporting portion; and

sealing material that seals the front surface of the conductive plate coated with the coating layer.

14 . The semiconductor device according to claim 13 , wherein in the upward direction, the supporting portion is disposed away from the front surface so that a lowest point of the supporting portion is at a level higher than the level of the front surface.

15 . The semiconductor device according to claim 14 , wherein the disposition area of the conductive plate is concave, and a bottom of the disposition area is located at a level lower than is the highest point of the supporting portion in the upward direction.

16 . The semiconductor device according to claim 14 , wherein

the highest point of the supporting portion of the conductive plate is located at a level higher than a level of the front surface in the upward direction, and

the semiconductor chip is bonded to the disposition area via the bonding material.

17 . The semiconductor device according to claim 16 , wherein the supporting portion is a wire extending in the periphery along the disposition area or is resist material applied to the periphery along the disposition area.

18 . The semiconductor device according to claim 16 , wherein a void is included in the bonding material at a side portion thereof, between the front surface of the conductive plate and the coating layer.

19 . The semiconductor device according to claim 14 , wherein a chip front surface of the semiconductor chip is located at a level higher than the highest point of the supporting portion in the upward direction.

20 . The semiconductor device according to claim 14 , wherein the coating layer is made of thermosetting resin as a main component thereof, and the thermosetting resin is polyamide resin, polyamide imide resin, or polyetherimide resin.

21 . The semiconductor device according to claim 14 , further comprising a multi-layer board including a flat board having a flat plate shape and the conductive plate, the conductive plate being provided on a front surface of the flat board in an area adjacent to a part of an outer periphery of the flat board, wherein

the disposition area is set on the front surface of the conductive plate in an area adjacent to the part of the outer periphery of the flat board, and

the supporting portion is provided in a portion of the periphery of the disposition area, the portion of the periphery of the disposition area facing the part of the outer periphery of the flat board.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2022
From: TAKAHASHI, YOSHIAKI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 060915/0387 →
Priority Claims (1)
JP 2021-168167 · Oct 13, 2021 · national
Continuity (1)
Related Publication 20230115598A1 · Apr 13, 2023
References Cited (15)
US 20100097431A1 · Takakuwa · 2010 [cited by examiner]
US 20110037153A1 · Zhu · 2011 [cited by examiner]
US 20120208324A1 · Harata · 2012 [cited by examiner]
US 20160276249A1 · Okada · 2016 [cited by applicant]
US 20190164807A1 · Wachtler · 2019 [cited by examiner]
US 20210305175A1 · Abe et al. · 2021 [cited by applicant]
JP H05047810A · 1993 [cited by applicant]
JP H10321666A · 1998 [cited by applicant]
JP H11145363A · 1999 [cited by applicant]
JP 2005302835A · 2005 [cited by applicant]
JP 2016174053A · 2016 [cited by applicant]
JP 2018207002A · 2018 [cited by applicant]
JP 2019071502A · 2019 [cited by applicant]
WO 2020017574A1 · 2020 [cited by applicant]
Japanese Patent Office Action issued for corresponding JP Patent Application No. 2021-168167 on Aug. 5, 2025. [cited by applicant]