Semiconductor structure
A semiconductor structure includes a first chip and a second chip bonded to the first chip. The first chip includes a first semiconductor substrate, a first multi-level interconnect structure over the first semiconductor substrate, a first redistribution layer (RDL) over a conductive line of the first multi-level interconnect structure, a compact layer over the first RDL and the first multi-level interconnect structure, a cap layer over the compact layer, and a metal pad on the first RDL. The second chip includes a second semiconductor substrate, a second multi-level interconnect structure over the second semiconductor substrate, and conductive structure extending from the second multi-level interconnect structure to the metal pad.
1 . A semiconductor structure, comprising:
a first chip comprising:
a first semiconductor substrate;
a first multi-level interconnect structure over the first semiconductor substrate, the first multi-level interconnect structure comprising a conductive line;
a first redistribution layer (RDL) over the conductive line of the first multi-level interconnect structure;
a compact layer over the first RDL and the first multi-level interconnect structure, wherein the compact layer has a portion within the first multi-level interconnect structure;
a cap layer over the compact layer; and
a metal pad on the first RDL; and
a second chip bonded to the first chip, the second chip comprising:
a second semiconductor substrate;
a second multi-level interconnect structure over the second semiconductor substrate; and
a conductive structure extending from the second multi-level interconnect structure to the metal pad.
2 . The semiconductor structure of claim 1 , wherein the compact layer is made of polymer or glass.
3 . The semiconductor structure of claim 1 , wherein the compact layer has dopants containing nitrogen, hydrogen or oxygen.
4 . The semiconductor structure of claim 1 , wherein the cap layer is in contact with the compact layer.
5 . The semiconductor structure of claim 1 , wherein the compact layer is in contact with the metal pad.
6 . The semiconductor structure of claim 1 , wherein the first chip further comprises a dielectric layer between the compact layer and the first multi-level interconnect structure.
7 . The semiconductor structure of claim 1 , wherein the cap layer is selected from the group consisting of silicon, carbon, oxygen, and nitrogen.
8 . The semiconductor structure of claim 1 , wherein the first RDL comprises:
a top portion;
a bottom portion; and
a neck portion between the top portion and the bottom portion, wherein the top portion is thicker than the bottom portion.
9 . The semiconductor structure of claim 8 , wherein the neck portion and the bottom portion of the first RDL are within the first multi-level interconnect structure.
10 . The semiconductor structure of claim 1 , wherein the second chip comprises a second RDL over the second multi-level interconnect structure.
11 . The semiconductor structure of claim 1 , wherein the second chip comprises a dielectric layer between the second semiconductor substrate and the cap layer, wherein the dielectric layer and the cap layer include a same material.
12 . A semiconductor structure, comprising:
a first chip comprising:
a first semiconductor substrate;
a first multi-level interconnect structure over the first semiconductor substrate, the first multi-level interconnect structure comprising a conductive line;
a first redistribution layer (RDL) over the conductive line of the first multi-level interconnect structure;
a compact layer over the first RDL and the first multi-level interconnect structure;
a cap layer over the compact layer; and
a metal pad on the first RDL, wherein the compact layer is in contact with the metal pad; and
a second chip bonded to the first chip, the second chip comprising:
a second semiconductor substrate;
a second multi-level interconnect structure over the second semiconductor substrate; and
a conductive structure extending from the second multi-level interconnect structure to the metal pad.