Post passivation structure for a semiconductor device and packaging process for same
A post passivation rerouting support structure comprises a relatively thin support layer above the passivation layer to support the RDL, and a relatively thick support layer for fine pitch interconnects extending from the RDL and terminating as contact structures at the surface of the thick support layer, for a next level packaging structure. The thick support layer is planarized before defining the contact structures. The thick support layer may be formed after the conducting posts have been formed, or the thick support layer is formed before forming the conducting posts in vias formed in the thick support layer. An encapsulating layer may be provided above the thick support layer, which top surface is planarized before defining the contact structures. The encapsulating layer and the further support layer may be the same layer.
1. An integrated circuit chip comprising:
a substrate;
a MOS device on said substrate;
a first contact pad over said substrate;
a second contact pad over said substrate;
a passivation layer over said substrate, wherein a first opening in said passivation layer is over a first contact point of said first contact pad, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said second contact pad, and said second contact point is at a bottom of said second opening, wherein said passivation layer comprises a nitride;
a patterned circuit layer over said passivation layer and on said first and second contact points, wherein said patterned circuit layer is connected to said first contact point through said first opening, and said patterned circuit layer is connected to said second contact point through said second opening, wherein said patterned circuit layer comprises a bottom metal layer over said passivation layer and on said first and second contact points, and electroplated copper directly over and in physical contact with said bottom metal layer;
a first metal post on and in physical contact with said patterned circuit layer, wherein said first metal post is connected to said first contact point through said patterned circuit layer, wherein said first metal post is not vertically over said first contact point, wherein said first metal post comprises electroplated copper and has a height between 25 and 200 micrometers;
a second metal post on and in physical contact with said patterned circuit layer, wherein said second metal post is connected to said second contact point through said patterned circuit layer, wherein said second metal post is not vertically over said second contact point, wherein said second metal post comprises electroplated copper and has a height between 25 and 200 micrometers, wherein a pitch between said first and second metal posts is less than 250 micrometers;
a first polymer layer over said passivation layer and on said patterned circuit layer, wherein said first metal post is in said first polymer layer and has a top surface not covered by said first polymer layer, and wherein said second metal post is in said first polymer layer and has a top surface not covered by said first polymer layer, wherein said top surface of said first metal post and said top surface of said second metal post are substantially coplanar with a top surface of said first polymer layer;
a UBM layer on said top surface of said first metal post and said top surface of said second metal post;
a first electroplated solder bump on said UBM layer and vertically over said top surface of said first metal post; and
a second electroplated solder bump on said UBM layer and vertically over said top surface of said second metal post.
2. The integrated circuit chip of claim 1 , wherein said UBM layer comprises titanium.
3. The integrated circuit chip of claim 1 further comprising a second polymer layer on said passivation layer, wherein said patterned circuit layer and said first polymer layer are further on said second polymer layer.
4. The integrated circuit chip of claim 1 , wherein said bottom metal layer comprises titanium.
5. The integrated circuit chip of claim 1 , wherein said bottom metal layer comprises copper.
6. An integrated circuit chip comprising:
a substrate;
a MOS device on said substrate;
a first contact pad over said substrate;
a second contact pad over said substrate;
a separating layer over said substrate, wherein a first opening in said separating layer is over a first contact point of said first contact pad, and said first contact point is at a bottom of said first opening, and wherein a second opening in said separating layer is over a second contact point of said second contact pad, and said second contact point is at a bottom of said second opening, wherein said separating layer comprises a nitride;
a patterned circuit layer over said separating layer and on said first and second contact points, wherein said patterned circuit layer is connected to said first contact point through said first opening, and said patterned circuit layer is connected to said second contact point through said second opening, wherein said patterned circuit layer comprises a bottom metal layer over said separating layer and on said first and second contact points, and electroplated copper directly over and in physical contact with said bottom metal layer;
a first metal post on and in physical contact with said patterned circuit layer, wherein said first metal post is connected to said first contact point through said patterned circuit layer, wherein said first metal post is not vertically over said first contact point, wherein said first metal post comprises electroplated copper and has a height between 25 and 200 micrometers;
a second metal post on and in physical contact with said patterned circuit layer, wherein said second metal post is connected to said second contact point through said patterned circuit layer, wherein said second metal post is not vertically over said second contact point, wherein said second metal post comprises electroplated copper and has a height between 25 and 200 micrometers, wherein a pitch between said first and second metal posts is less than 250 micrometers; and
a first polymer layer over said separating layer and on said patterned circuit layer, wherein said first metal post is in said first polymer layer and has a top surface not covered by said first polymer layer, and wherein said second metal post is in said first polymer layer and has a top surface not covered by said first polymer layer, wherein said top surface of said first metal post and said top surface of said second metal post are substantially coplanar with a top surface of said first polymer layer.
7. The integrated circuit chip of claim 6 further comprising a second polymer layer on said separating layer, wherein said patterned circuit layer and said first polymer layer are further on said second polymer layer.
8. The integrated circuit chip of claim 6 , wherein said bottom metal layer comprises titanium.
9. The integrated circuit chip of claim 6 , wherein said bottom metal layer comprises copper.
10. The integrated circuit chip of claim 6 further comprising a second polymer layer on said first polymer layer, wherein a third opening in said second polymer layer is over said top surface of said first metal post, and a fourth opening in said second polymer layer is over said top surface of said second metal post.
11. An integrated circuit chip comprising:
a substrate;
a MOS device on said substrate;
a contact pad over said substrate;
a passivation layer over said substrate, wherein an opening in said passivation layer is over a contact point of said contact pad, and said contact point is at a bottom of said opening, wherein said passivation layer comprises a nitride;
a patterned circuit layer over said passivation layer and on said contact point, wherein said patterned circuit layer is connected to said contact point through said opening, wherein said patterned circuit layer comprises a bottom metal layer over said passivation layer and on said contact point, and electroplated copper directly over and in physical contact with said bottom metal layer;
a metal post on and in physical contact with said patterned circuit layer, wherein said metal post is connected to said contact point through said patterned circuit layer, wherein said metal post is not vertically over said contact point, wherein said metal post comprises electroplated copper and has a height between 25 and 200 micrometers;
a first polymer layer over said passivation layer and on said patterned circuit layer, wherein said metal post is in said first polymer layer and has a top surface not covered by said first polymer layer, wherein said top surface of said metal post is substantially coplanar with a top surface of said first polymer layer;
a UBM layer on said top surface of said metal post; and
an electroplated solder bump on said UBM layer and vertically over said top surface of said metal post, wherein said integrated circuit chip has a pin count of greater than 400.
12. The integrated circuit chip of claim 11 , wherein said UBM layer comprises titanium.
13. The integrated circuit chip of claim 11 further comprising a second polymer layer on said passivation layer, wherein said patterned circuit layer and said first polymer layer are further on said second polymer layer.
14. The integrated circuit chip of claim 11 , wherein said bottom metal layer comprises titanium.
15. The integrated circuit chip of claim 11 , wherein said bottom metal layer comprises copper.
16. An integrated circuit chip comprising:
a substrate;
a MOS device on said substrate;
a first contact pad over said substrate;
a second contact pad over said substrate;
a passivation layer over said substrate, wherein a first opening in said passivation layer is over a first contact point of said first contact pad, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said second contact pad, and said second contact point is at a bottom of said second opening, wherein said passivation layer comprises a nitride;
a patterned circuit layer over said passivation layer and on said first and second contact points, wherein said patterned circuit layer is connected to said first contact point through said first opening, and said patterned circuit layer is connected to said second contact point through said second opening, wherein said patterned circuit layer comprises a bottom metal layer over said passivation layer and on said first and second contact points, and electroplated copper directly over and in physical contact with said bottom metal layer;
a first metal post on and in physical contact with said patterned circuit layer, wherein said first metal post is connected to said first contact point through said patterned circuit layer, wherein said first metal post is not vertically over said first contact point, wherein said first metal post comprises electroplated copper and has a height between 25 and 200 micrometers;
a second metal post on and in physical contact with said patterned circuit layer, wherein said second metal post is connected to said second contact point through said patterned circuit layer, wherein said second metal post is not vertically over said second contact point, wherein said second metal post comprises electroplated copper and has a height between 25 and 200 micrometers, wherein a pitch between said first and second metal posts is less than 250 micrometers; and
a first polymer layer over said passivation layer and on said patterned circuit layer, wherein said first metal post is in said first polymer layer and has a top surface not covered by said first polymer layer, and wherein said second metal post is in said first polymer layer and has a top surface not covered by said first polymer layer, wherein said top surface of said first metal post and said top surface of said second metal post are substantially coplanar with a top surface of said first polymer layer, wherein said integrated circuit chip has a pin count of greater than 400.
17. The integrated circuit chip of claim 16 further comprising a second polymer layer on said first polymer layer, wherein a third opening in said second polymer layer is over said top surface of said first metal post, and a fourth opening in said second polymer layer is over said top surface of said second metal post.
18. The integrated circuit chip of claim 16 further comprising a second polymer layer on said passivation layer, wherein said patterned circuit layer and said first polymer layer are further on said second polymer layer.
19. The integrated circuit chip of claim 16 , wherein said bottom metal layer comprises titanium.
20. The integrated circuit chip of claim 16 , wherein said bottom metal layer comprises copper.