IP Library › Granted Patent US 12,486,159
Granted Patent B2
US 12,486,159 · App. 17/364,381 · Granted Dec 2, 2025

Micro-machined ultrasound transducers with insulation layer and methods of manufacture

Inventors: Naresh Mantravadi (San Jose, CA); Haesung Kwon (Austin, TX); Brian Bircumshaw (Oakland, CA)
Assignee: Exo Imaging, Inc.
B81B3/0021B06B1/0292B06B1/0603B81C1/00158B81B2201/0271B81B2203/0127B81B2203/0315B81B2207/07B81C2201/0132B81C2203/036
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Quick Facts
Patent No.
US 12,486,159
App. No.
17/364,381
Granted
Dec 2, 2025
Kind
B2
Abstract

Disclosed is a multi-silicon on insulator (SOI) micromachined ultrasonic transducer (MUT) device. The device comprises a multi-SOI substrate and a MUT. The MUT is affixed to a surface of the multi-SOI substrate. The multi-SOI substrate has a first SOI layer and at least a second SOI layer disposed above the first SOI layer. The first SOI layer and the second SOI layer each comprise an insulating layer and a semiconducting layer. The first SOI layer further defines a cavity located under a membrane of a MUT and one or more trenches at least partially around a perimeter of the cavity.

Claims (27)

1 . A multi-silicon on insulator (SOI) micromachined ultrasonic transducer (MUT) device comprising:

a multi-SOI substrate comprising a first SOI layer and a second SOI layer disposed above the first SOI layer, such that the second SOI layer forms a top surface of the multi-SOI substrate; and

a MUT comprising a membrane and being affixed to the top surface of the multi-SOI substrate,

wherein each of the first SOI layer and the second SOI layer comprises an insulating layer and a semiconducting layer,

wherein the first SOI layer further comprises a cavity and one or more trenches, the cavity being located under the membrane of the MUT and having a first depth, and the one or more trenches being located at least partially around a perimeter of the cavity and having a second depth that at least partially overlaps the first depth within the multi-SOI substrate.

2 . The device of claim 1 , wherein the MUT is a piezoelectric micromachined ultrasound transducer (pMUT).

3 . The device of claim 1 , wherein the MUT is a capacitive micromachined ultrasound transducer (cMUT).

4 . The device of claim 1 , wherein the second SOI layer is 40-80 micrometers in height.

5 . The device of claim 1 , wherein the insulating layer is a buried oxide (BOX) layer.

6 . The device of claim 5 , wherein the BOX layer is 1-5 micrometers in height.

7 . The device of claim 5 , wherein the semiconducting layers of the first SOI layer and at least the second SOI layer are handle layers, and wherein the cavity is created by etching at least one of the handle layers and the BOX layer.

8 . The device of claim 1 , further including a through silicon via.

9 . The device of claim 1 , wherein the semiconducting layer is a silicon membrane layer.

10 . The device of claim 1 , wherein the multi-SOI substrate is a double-SOI substrate.

11 . The device of claim 1 , wherein the cavity includes a deposited oxide layer.

12 . The device of claim 1 , wherein each of the one or more trenches is etched to a depth spanning one or more layers of the device.

13 . The device of claim 1 , further comprising a handle layer below the first SOI layer.

14 . The device of claim 13 , wherein the handle layer is a semiconductor layer.

15 . The device of claim 1 , wherein the semiconducting layer of the second SOI layer includes a metallic coating.

16 . The device of claim 1 , wherein the cavity is filled with a gas.

17 . The device of claim 1 , wherein the cavity is maintained under vacuum pressure.

18 . The device of claim 1 , wherein the insulating layer comprises a non-oxide insulator.

19 . A multi-silicon on insulator (SOI) micromachined ultrasonic transducer (MUT) array comprising:

a multi-SOI substrate comprising a first SOI layer and a second SOI layer disposed above the first SOI layer, such that the second SOI layer forms a top surface of the multi-SOI substrate; and

a MUT having comprising a membrane and being affixed to the top surface of the multi-SOI substrate,

wherein each of the first SOI layer and the second SOI layer comprises an insulating layer and a semiconducting layer,

wherein the first SOI layer further comprises a cavity and one or more trenches, the cavity being located under the membrane of the MUT and having a first depth, and the one or more trenches being located at least partially around a perimeter of the cavity and having a second depth that at least partially overlaps the first depth within the multi-SOI substrate.

Assignments (2)
SECURITY INTEREST Recorded Dec 4, 2025
From: EXO IMAGING, INC.
To: WTI FUND X, INC.; WTI FUND XI, INC.
Reel/Frame 073852/0075 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2021
From: MANTRAVADI, NARESH; KWON, HAESUNG; BIRCUMSHAW, BRIAN
To: EXO IMAGING, INC.
Reel/Frame 058525/0541 →
Continuity (1)
Related Publication 20230002213A1 · Jan 5, 2023
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