Reference markers adjacent to a cavity in a photonics chip
Structures including a cavity adjacent to an edge coupler and methods of forming such structures. The structure comprises a semiconductor substrate including a cavity with a sidewall, a dielectric layer on the semiconductor substrate, and an edge coupler on the dielectric layer. The structure further comprises a fill region including a plurality of fill features adjacent to the edge coupler. The fill region includes a reference marker at least partially surrounded by the plurality of fill features, and the reference marker has a perimeter that surrounds a surface area of the dielectric layer, and the surface area overlaps with a portion of the sidewall of the cavity.
1 . A structure comprising:
a semiconductor substrate including a cavity with a first sidewall;
a first dielectric layer on the semiconductor substrate;
an edge coupler on the first dielectric layer;
a fill region including a plurality of fill features adjacent to the edge coupler, the fill region including a first reference marker partially surrounded by the plurality of fill features, the first reference marker having a perimeter that surrounds a first surface area of the first dielectric layer, and the first surface area overlapping with a portion of the first sidewall of the cavity;
a back-end-of-line stack including a stack of interlayer dielectric layers over the first dielectric layer; and
a second dielectric layer over the edge coupler, the second dielectric layer converging with the back-end-of-line stack along an interface.
2 . The structure of claim 1 wherein the plurality of fill features are absent inside the perimeter of the first reference marker.
3 . The structure of claim 1 wherein the first sidewall adjoins the first dielectric layer along an edge, and the perimeter of the first reference marker overlaps with a portion of the edge.
4 . The structure of claim 1 wherein the first dielectric layer includes a first edge adjacent to the edge coupler, the cavity includes an undercut region that extends in the semiconductor substrate from the first edge of the first dielectric layer beneath the edge coupler, and the perimeter of the first reference marker overlaps with a portion of the first edge in the undercut region.
5 . The structure of claim 4 wherein the first sidewall of the cavity adjoins the first dielectric layer along a second edge, and the perimeter of the first reference marker overlaps with a portion of the second edge.
6 . The structure of claim 1 wherein the edge coupler is directly positioned on the first dielectric layer, and the fill region is directly positioned on the first dielectric layer.
7 . The structure of claim 6 wherein the plurality of fill features and the edge coupler comprise the same material.
8 . The structure of claim 1 further comprising:
a third dielectric layer on the first dielectric layer,
wherein the edge coupler is embedded in the third dielectric layer, the third dielectric layer is positioned between the first dielectric layer and the second dielectric layer, and the fill region is positioned on the second dielectric layer.
9 . The structure of claim 8 wherein the plurality of fill features comprise a first material, and the edge coupler comprises a second material different from the first material.
10 . The structure of claim 1 wherein the cavity has a second sidewall, the fill region includes a second reference marker partially surrounded by the plurality of fill features, the second reference marker has a perimeter that surrounds a second surface area of the first dielectric layer, and the second surface area overlaps with the second sidewall of the cavity.
11 . The structure of claim 10 wherein the plurality of fill features are absent inside the perimeter of the first reference marker, and the plurality of fill features are absent inside the perimeter of the second reference marker.
12 . The structure of claim 10 wherein the cavity includes an undercut region that extends beneath the first dielectric layer, the first dielectric layer includes an edge adjacent to the edge coupler, and the first reference marker is spaced along the edge from the second reference marker.
13 . The structure of claim 10 wherein the first sidewall of the cavity adjoins the first dielectric layer along a first edge, the perimeter of the first reference marker overlaps with a portion of the first edge, the second sidewall of the cavity adjoins the first dielectric layer along a second edge, and the perimeter of the second reference marker overlaps with a portion of the second edge.
14 . The structure of claim 13 wherein the cavity has a width dimension that extends from the first edge to the second edge.
15 . The structure of claim 10 wherein the cavity includes a trench bottom that connects the first sidewall to the second sidewall, and the trench bottom is positioned between the first reference marker and the second reference marker.
16 . The structure of claim 1 further comprising:
a light source positioned in the cavity adjacent to the edge coupler, the light source having a light output configured to provide light in a mode propagation direction toward the edge coupler.
17 . The structure of claim 16 wherein the cavity is a groove having an open end, and the light source is an optical fiber.
18 . The structure of claim 1 further comprising:
a third dielectric layer on the first dielectric layer,
wherein the third dielectric layer comprises a dielectric material, the third dielectric layer is positioned between the first dielectric layer and the second dielectric layer, and the dielectric material of the third dielectric layer is positioned on the first surface area of the first dielectric layer inside the perimeter of the first reference marker.
19 . The structure of claim 1 wherein the edge coupler includes a waveguide core, and the first reference marker is positioned adjacent to a portion of the waveguide core.
20 . A method comprising:
forming a cavity in a semiconductor substrate, wherein the cavity includes a sidewall, and a first dielectric layer is positioned on the semiconductor substrate;
forming an edge coupler on the first dielectric layer;
forming a fill region including a plurality of fill features adjacent to the edge coupler and the cavity, wherein the fill region includes a reference marker partially surrounded by the plurality of fill features, the reference marker has a perimeter that surrounds a surface area of the first dielectric layer, and the surface area overlaps with a portion of the sidewall of the cavity;
forming a back-end-of-line stack including a stack of interlayer dielectric layers over the first dielectric layer;
removing a portion of the back-end-of-line stack from over the edge coupler; and
forming a second dielectric layer over the edge coupler to replace the portion of the back-end-of-line stack, wherein the second dielectric layer and the back-end-of-line stack converge along an interface.