Module with high peak bandwidth I/O channels
A high peak bandwidth I/O channel embedded within a multilayer surface interface that forms the bus circuitry electrically interfacing the output or input port on a first semiconductor die with the input or output port on a second semiconductor die.
1 . A circuit module comprising a high peak bandwidth I/O channel formed upon a substrate upon which semiconductor die are attached, wherein the high peak bandwidth I/O channel comprises a multilayer surface interface that further comprises:
conducting means that forms a channel link within a data signal plane that electrically interfaces signal transmission between the vias that form an electrical connection with input/output ports of semiconductor die mounted upon the substrate;
low permittivity/ultra-low loss dielectric that envelopes the channel link;
additional conductive means to form power planes and ground planes that separate, and,
a passive network filtering circuit comprising capacitive, inductive, and resistive elements embedded within the high peak bandwidth I/O channel,
wherein,
the passive network filtering circuit elements further comprises high energy density electroceramic dielectric that polarizes and depolarizes with femto-second response times.
2 . The circuit module of claim 1 , wherein the substrate is a semiconductor.
3 . The circuit module of claim 2 , wherein the semiconductor substrate is a semiconductor carrier.
4 . The circuit module of claim 2 , wherein the multilayer surface interface comprises a signal control plane that electrically interfaces with active circuitry embedded within the active plane of the semiconductor substrate.
5 . The circuit module of claim 3 , wherein the active circuitry embedded within the active plane comprises an Op-Amp.
6 . The circuit module of claim 5 , wherein the Op-Amp is in electrical communication with passive circuit elements embedded within the multilayer surface interface.
7 . The circuit module of claim 6 , wherein the Op-Amp and embedded passive circuit elements form a fully integrated gyrator circuit.
8 . The circuit module of claim 7 , wherein the fully integrated gyrator circuit functions an inductive element.
9 . The circuit module of claim 7 , wherein the fully integrated gyrator functions as a network filter.
10 . The circuit module of claim 7 , wherein the fully integrated gyrator functions as a loss-less transformer.
11 . The circuit module of claim 4 , wherein the active circuitry embedded within the active plane comprises a resonant gate transistor.
12 . The circuit module of claim 4 , wherein the active circuit embedded within the active plane comprises a resonant gate transistor and active switching elements.
13 . The circuit module of claim 1 , wherein a semiconductor die are heterogeneously mounted on the substrate surface.
14 . The circuit module of claim 1 , wherein a plurality of semiconductor are embedded within a chip stack assembly.
15 . The circuit module of claim 14 , wherein the chip stack assembly comprises a high peak bandwidth I/O channel.
16 . The circuit module of claim 1 , wherein the semiconductor die are used to manage any or all of the following circuit functions:
memory, memory controller, device controller, central processor unit, graphical processor, stack processor, quantum processor;
arrayed gate field programmability, radio connectivity, optical field imaging, radiation field imaging, electro-optical imaging;
and,
application-specific integrated (ASIC) circuitry.
17 . The circuit module of claim 16 , wherein a semiconductor die is used to function as an imaging device that digitally captures electromagnetic fields at clock speeds in excess of 3 GHz, preferably in excess of 100 GHz, and most preferably at 1 THz.
18 . The circuit module of claim 16 , wherein memory functionality comprises read-only memory, random access memory, dynamic random access memory, static dynamic random access memory, nonvolatile memory, ferroelectric random access memory, optical memory, resistive-element random access memory.
19 . A circuit module as in claim 1 , wherein the high peak bandwidth I/O link additionally comprises vias that form an electrical interface with input and output ports to a semiconductor chip carrier in electrical communication with circuit modules.
20 . The circuit module of claim 1 , wherein the passive network filtering circuit functions as a termination circuit.
21 . The circuit module of claim 1 , wherein the passive network filtering circuit functions as an equalization circuit.
22 . The circuit module of claim 21 , wherein the equalization circuit functions in Pre-Emphasis mode, Post-Emphasis mode, or both Pre-Emphasis and Post-Emphasis modes.