IP Library › Granted Patent US 12,494,376
Granted Patent B2
US 12,494,376 · App. 17/903,417 · Granted Dec 9, 2025

Control method of multi-stage etching process and processing device using the same

Inventors: Liang Ju Wei (Chiayi, TW); Chung-Yi Chiu (Tainan, TW); Zhen Wu (Kaohsiung, TW); Hsuan-Hsu Chen (Tainan, TW); Chun-Lung Chen (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L21/32139H01J37/32926H01J2237/334
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Quick Facts
Patent No.
US 12,494,376
App. No.
17/903,417
Granted
Dec 9, 2025
Kind
B2
Abstract

A control method of a multi-stage etching process and a processing device using the same are provided. The control method of the multi-stage etching process includes the following step S. A stack information of a plurality of hard mask layers is set. An etching target condition is set. Through a machine learning model, a parameter setting recipe of the hard mask layers is generated under the etching target condition. The machine learning model is trained based on the stack information of the hard mask layers, a plurality of process parameters and a process result.

Claims (13)

1 . A control method of a multi-stage etching process, comprising:

receiving, by a multi-layer setting circuit, a stack information of a plurality of hard mask layers, wherein the stack information includes materials of the hard mask layers, thicknesses of the hard mask layers and stacking sequence of the hard mask layers;

receiving, by a target setting circuit, an etching target condition; and

receiving, by a machine learning model circuit, the stack information and the etching target condition to generate a parameter setting recipe of the hard mask layers through machine learning, wherein the machine learning circuit is trained based on the stack information of the hard mask layers including the materials of the hard mask layers, the thicknesses of the hard mask layers and the stacking sequence of the hard mask layers, a plurality of process parameters, and a process result, and wherein the stack information includes the materials of the hard mask layers, the thicknesses of the hard mask layers and the stacking sequence of the hard mask layers; and

etching the hard mask layers based on the parameter setting recipe.

2 . The control method of the multi-stage etching process according to claim 1 , wherein the etching target condition is an etching rate, an edge profile or a critical dimension.

3 . The control method of the multi-stage etching process according to claim 1 , wherein the parameter setting recipe is a gas flow, a bias RF power or an E-chuck temperature.

4 . The control method of the multi-stage etching process according to claim 1 , wherein the etching target condition is set for one of the hard mask layers.

5 . The control method of the multi-stage etching process according to claim 1 , wherein the etching target condition is set for more than two of the hard mask layers which are adjacent.

6 . The control method of the multi-stage etching process according to claim 1 , wherein the etching target condition is set for whole of the hard mask layers.

7 . The control method of the multi-stage etching process according to claim 1 , wherein the parameter setting recipe is set for one of the hard mask layers.

8 . The control method of the multi-stage etching process according to claim 1 , wherein the parameter setting recipe is set for more than two of the hard mask layers which are adjacent.

9 . The control method of the multi-stage etching process according to claim 1 , wherein the parameter setting recipe is set for whole of the hard mask layers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2022
From: WEI, LIANG JU; CHIU, CHUNG-YI; WU, ZHEN; CHEN, HSUAN-HSU; CHEN, CHUN-LUNG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 060997/0006 →
Priority Claims (1)
TW 111129157 · Aug 3, 2022 · national
Continuity (1)
Related Publication 20240047225A1 · Feb 8, 2024
References Cited (4)
US 7596422B2 · Chard · 2009 [cited by applicant]
US 8747684B2 · Srinivasan · 2014 [cited by applicant]
US 8907456B2 · Wei · 2014 [cited by examiner]
WO WO2017049175A1 · 2017 [cited by examiner]