IP Library › Granted Patent US 12,494,397
Granted Patent B2
US 12,494,397 · App. 17/863,932 · Granted Dec 9, 2025

Semiconductor device and method for fabricating the same

Inventor: Jun Sik Kim (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
H01L21/764H01L21/76834H10B12/482H10B12/488
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Quick Facts
Patent No.
US 12,494,397
App. No.
17/863,932
Granted
Dec 9, 2025
Kind
B2
Abstract

A semiconductor device comprises a lower structure; a plurality of semiconductor layers laterally oriented in a direction parallel to a surface of the lower structure; a plurality of bit lines connected an end of the semiconductor layers and extending in a direction perpendicular to the surface of the lower structure; word lines extending laterally in a direction crossing the semiconductor layers over the semiconductor layers; and a device isolation layer extending in the direction parallel to the surface of the lower structure to be disposed between the bit lines and the word lines and including air gaps.

Claims (22)

1 . A semiconductor device comprising:

a lower structure;

a plurality of semiconductor layers laterally oriented in a direction parallel to a surface of the lower structure;

a plurality of bit lines connected to an end of the semiconductor layers and extending in a direction perpendicular to the surface of the lower structure;

word lines extending laterally in a direction crossing the semiconductor layers over the semiconductor layers; and

a device isolation layer extending in the direction parallel to the surface of the lower structure to be disposed between the bit lines and the word lines and including air gaps;

wherein the device isolation layer further includes a capping layer capping an upper portion of the air gaps, wherein the air gaps directly contact a sidewall of the word lines.

2 . The semiconductor device of claim 1 ,

wherein the device isolation layer includes silicon oxide, silicon carbon oxide, silicon nitride, or a combination thereof.

3 . A semiconductor device comprising:

a lower structure;

a plurality of active layers extending in a direction parallel to a surface of the lower structure;

word lines extending laterally in a direction crossing the active layers over the active layers;

a plurality of bit lines connected to an end of the active layers and extending in a direction perpendicular to the surface of the lower structure;

a plurality of capacitors connected to an opposite end of the active layers; and

a device isolation layer including air gaps, the air gaps being disposed between the bit lines and the word lines;

wherein the device isolation layer further includes a capping layer capping an upper portion of the air gaps;

wherein the air gaps directly contact a sidewall of the word lines.

4 . The semiconductor device of claim 3 , wherein the device isolation layer includes silicon oxide, silicon carbon oxide, silicon nitride, or a combination thereof.

5 . The semiconductor device of claim 3 , wherein the air gaps extend vertically from the lower structure.

6 . The semiconductor device of claim 3 , wherein each of the word lines includes a double word line.

7 . The semiconductor device of claim 3 , wherein each of the active layers includes a silicon layer, a monocrystalline silicon layer, a polysilicon layer, or an oxide semiconductor material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2022
From: KIM, JUN SIK
To: SK HYNIX INC.
Reel/Frame 060497/0090 →
Priority Claims (1)
KR 10-2022-0014881 · Feb 4, 2022 · national
Continuity (1)
Related Publication 20230253242A1 · Aug 10, 2023
References Cited (12)
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Office Action for Korean Patent Application No. 10-2022-0014881 issued by the Korean Patent Office on Aug. 11, 2025. [cited by applicant]