Semiconductor device with through-mold via
A semiconductor device includes a substrate with a conductive pattern. A semiconductor die is electrically connected to the substrate and both the semiconductor die and the substrate are at least partially covered by a package body. In some examples, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In some examples, through-mold vias are included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body. In some examples, an interposer is electrically connected to the through-mold vias and may be covered by the package body and/or disposed in spaced relation thereto. In some examples, the interposer may not be electrically connected to the through-mold vias but may have one or more semiconductor dies of the semiconductor device electrically connected thereto.
1 . A method of manufacturing a semiconductor device, comprising:
providing a substrate comprising a top major surface and a bottom major surface opposite to the top major surface;
providing an electrically conductive pattern adjoining the top major surface;
providing conductive lands adjoining the bottom major surface and including a first conductive land, a second conductive land, a third conductive land, and a fourth conductive land;
providing conductive vias within the substrate and connecting part of the electrically conductive pattern to the conductive lands, the conductive vias including a first conductive via comprising a first width in a cross-sectional view and connected to the third conductive land;
providing conductive bumps;
providing a first semiconductor die mounted to the first conductive land and the second conductive land with the conductive bumps;
providing an electronic component electrically connected to the electrically conductive pattern of the substrate and mounted on the top major surface of the substrate;
providing a first package body encapsulating the first semiconductor die and comprising a bottom exterior surface distal to the bottom major surface of the substrate;
providing a second package body encapsulating the electronic component;
providing a first electrically conductive path physically and electrically connected to the third conductive land and extending to the bottom exterior surface of the first package body comprising a second width in the cross-sectional view that is greater than the first width; and
providing a second electrically conductive path physically and electrically connected to the fourth conductive land and extending to the bottom exterior surface of the first package body, wherein:
the first electrically conductive path comprises a first outer surface exposed from the bottom exterior surface of the first package body and configured as a first external electrical interconnect structure; and
the second electrically conductive path comprises a second outer surface exposed from the bottom exterior surface of the first package body and configured as a second external electrical interconnect structure.
2 . The method of claim 1 , wherein:
providing the conductive vias comprises providing the first conductive via is laterally offset with respect to the first electrically conductive path in the cross-sectional view;
providing the first electrically conductive path comprises providing a first conductive via; and
providing the second electrically conductive path comprises providing a second conductive via.
3 . The method of claim 1 , further comprising:
providing a bond pad on the electronic component; and
providing a conductive interconnect directly connecting the bond pad to the electrically conductive pattern;
wherein:
providing the second package body comprises providing the second package body encapsulating the conductive interconnect and contacting the bond pad;
providing the first electrically conductive path comprises providing a first reflowed conductive ball; and
providing the second electrically conductive path comprises providing a second reflowed conductive ball.
4 . The method of claim 1 , further comprising:
providing the first semiconductor die including a first side, a second side opposite to the first side, and a first bond pad over the first side; and
mounting the first bond pad to the first conductive land with a first conductive bump of the conductive bumps.
5 . The method of claim 1 , further comprising:
providing a third electrically conductive path extending vertically from the top major surface of the substrate towards a top exterior surface of the second package body; and
providing a fourth electrically conductive path extending vertically from the top major surface of the substrate towards to the top exterior surface of the second package body, wherein:
providing the electronic component comprising providing the electronic component interposed between the third electrically conductive path and the fourth electrically conductive path in a cross-sectional view.
6 . The method of claim 5 , wherein:
providing the third electrically conductive path comprises:
providing a third conductive via comprising a third outer surface exposed from the top exterior surface of the second package body; and
providing the fourth electrically conductive path comprises:
providing a fourth conductive via comprising a fourth outer surface exposed from the top exterior surface of the second package body.
7 . The method of claim 1 , wherein:
providing the first semiconductor die comprises coupling the first semiconductor die to one or more of the first electrically conductive path and the second electrically conductive path.
8 . A method of manufacturing a semiconductor device comprising:
providing a substrate comprising an electrically conductive pattern disposed adjacent to a top side and conductive lands disposed adjacent to a bottom side opposite to the top side, wherein the electrically conductive pattern and the conductive lands are electrically connected to each other;
providing a first semiconductor die electrically connected to the conductive lands of the substrate and directly mounted to the bottom side of the substrate;
providing an electronic component electrically connected to the electrically conductive pattern of the substrate and mounted to the top side of the substrate;
providing a first package body encapsulating the first semiconductor die;
providing a second package body encapsulating the electronic component, wherein:
the first semiconductor die is interposed between a bottom exterior surface of the first package body and the bottom side of the substrate; and
the electronic component is interposed between a top exterior surface of the second package body and the top side of the substrate; and
providing a first conductive via structure comprising a first conductive via portion and a second conductive via portion, wherein:
the first conductive via portion extends from a first conductive land towards the bottom exterior surface of the first package body;
the second conductive via portion extends from a second conductive land towards the bottom exterior surface of the first package body;
the first conductive via portion comprises a first outer surface exposed by the bottom exterior surface of the first package body and configured as a first external electrical interconnect structure; and
the second conductive via portion comprises a second outer surface exposed by the bottom exterior surface of the first package body and configured as a second external electrical interconnect structure.
9 . The method of claim 8 , wherein:
providing the first conductive via portion comprises providing a first single continuous conductive structure that extends from the first conductive land to the bottom exterior surface of the first package body;
providing the second conductive via portion comprises providing a second single continuous conductive structure that extends from the second conductive land to the bottom exterior surface of the first package body; and
providing the first semiconductor die comprises interposing the first semiconductor die between the first conductive via portion and the second conductive via portion.
10 . The method of claim 8 , wherein:
providing the substrate comprises providing a substrate that is other than a semiconductor die; and
providing the first semiconductor die comprises mounting the first semiconductor die to the conductive lands with conductive bumps.
11 . The method of claim 8 , further comprising:
providing a second conductive via structure comprising:
a third conductive via portion extending from a first portion of the electrically conductive pattern towards the top exterior surface of the second package body; and
a third outer surface exposed in the top exterior surface of the second package body.
12 . The method of claim 11 , wherein:
providing the second conductive via structure comprises:
providing a fourth conductive via portion extending from a second portion of the electrically conductive pattern towards the top exterior surface of the second package body and comprising a fourth outer surface exposed in the top exterior surface of the second package body; and
providing the electronic component comprises providing the electronic component interposed between the third conductive via portion and the fourth conductive via portion in a cross-sectional view.
13 . The method of claim 8 , wherein:
the first package body comprises first exterior side surfaces extending generally perpendicularly between the bottom exterior surface of the first package body and the substrate;
the second package body comprises second exterior side surface extending generally perpendicularly between the top exterior surface of the second package body and the substrate; and
the first exterior side surfaces and second exterior side surfaces are generally co-planar with side surfaces of the substrate.
14 . A method of manufacturing a semiconductor device comprising:
providing a substrate comprising:
a top major surface and a bottom major surface opposite to the top major surface;
an electrically conductive pattern provided on the top major surface;
conductive lands provided on the bottom major surface including a first conductive land and a second conductive land; and
conductive vias provided within the substrate electrically connecting portions of the electrically conductive pattern to the conductive lands, the conductive vias including a first conductive via connected to the first conductive land, wherein the first conductive via comprises a first width in a cross-sectional view;
providing a semiconductor component that has first bond pads provided on the semiconductor component;
providing conductive bumps directly connecting the first bond pads to the conductive lands other than the first conductive land and the second conductive land;
providing an electronic component mounted on the top major surface of the substrate that has a second bond pad provided on the electronic component;
providing a conductive interconnect directly connecting the second bond pad to the electrically conductive pattern;
providing a first package body portion encapsulating the semiconductor component, the conductive bumps, and at least portions of the bottom major surface of the substrate and comprising a bottom exterior surface distal to the bottom major surface of the substrate;
providing a second package body portion encapsulating the conductive interconnect and the electronic component;
providing a first electrically conductive path physically and electrically connected to the first conductive land and comprising a first outer surface exposed from the bottom exterior surface, wherein the first electrically conductive path comprises a second width in the cross-sectional view that is greater than the first width; and
providing a second electrically conductive path physically and electrically connected to the second conductive land and comprising a second outer surface exposed from the bottom exterior surface, wherein:
the second package body portion contacts the top major surface of the substrate; and
the bottom exterior surface of the first package body portion is exposed outside of the semiconductor device.
15 . The method of claim 14 , further comprising:
providing a third electrically conductive path coupled to and extending vertically upwards from the top major surface of the substrate; and
providing a fourth electrically conductive path coupled to and extending vertically upwards from the top major surface of the substrate;
wherein:
providing the second package body portion comprises providing the second package body portion encapsulating at least portions of the third electrically conductive path and at least portions of the fourth electrically conductive path.
16 . The method of claim 15 , wherein:
providing the electronic component comprises providing the electronic component between the third electrically conductive path and the fourth electrically conductive path.
17 . The method of claim 15 , wherein:
providing one or more of the first electrically conductive path, the second electrically conductive path, the third electrically conductive path, or the fourth electrically conductive path comprise providing a via filled with a conductive material.
18 . The method of claim 15 , wherein:
providing the third electrically conductive path comprises providing the third electrically conductive path with a third outer surface exposed from a top exterior surface of the second package body portion.
19 . The method of claim 14 , wherein:
providing the first conductive via comprising providing the first conductive via laterally offset with respect to the first electrically conductive path in the cross-sectional view; and
providing the electrically conductive pattern comprises providing the electrically conductive pattern with portions that laterally overlap onto the top major surface of the substrate.
20 . The method of claim 14 , wherein:
providing the first package body portion comprises providing the first package body including a first thickness that defines the bottom exterior surface; and
providing the first package body comprises confining the semiconductor component, first electrically conductive path, and the second electrically conductive path within the first thickness.