IP Library Granted Patent US 12,494,460
Granted Patent B2
US 12,494,460 · App. 17/975,455 · Granted Dec 9, 2025

Electronic package and manufacturing method thereof

Inventors: Chung-Yu Ke (Taichung, TW); Liang-Pin Chen (Taichung, TW)
Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
H01L25/105H01L24/16H01L24/24H01L25/50H01L24/32H01L24/73H01L2224/16227H01L2224/24137H01L2224/244H01L2224/32225H01L2224/73204H01L2224/73259H01L2224/73267H01L2225/1035
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Quick Facts
Patent No.
US 12,494,460
App. No.
17/975,455
Granted
Dec 9, 2025
Kind
B2
Abstract

An electronic package is provided, in which an electronic module and a plurality of conductive pillars are embedded in an encapsulation layer, and a circuit structure is formed on the encapsulation layer, where the electronic module includes a carrier structure having conductive vias and at least a first electronic element disposed on the carrier structure. The first electronic element has a plurality of conductors in a form of conductive through-silicon vias, and at least a second electronic element is disposed on the circuit structure. Therefore, the design of the electronic module can reduce the layout area occupied by the electronic element on a surface of a packaging zone of the circuit structure, such that other functional elements can be added to the electronic package according to requirements, and the electronic package can improve functional requirements of the end product.

Claims (31)

1 . An electronic package, comprising:

an encapsulation layer having a first surface and a second surface opposing the first surface;

an electronic module embedded in the encapsulation layer and comprising a carrier structure and at least a first electronic element disposed on the carrier structure, wherein the first electronic element has a plurality of conductors penetrating through a surface of the first electronic element, wherein the carrier structure has a first side, a second side opposing the first side and a plurality of conductive vias communicating the first side and the second side, and wherein the first electronic element is disposed on the first side of the carrier structure and electrically connected to the plurality of conductive vias;

a plurality of conductive pillars embedded in the encapsulation layer;

a first circuit structure bonded with the first surface of the encapsulation layer and electrically connected to the plurality of conductive vias and the plurality of conductive pillars;

a second circuit structure bonded with the second surface of the encapsulation layer and electrically connected to the plurality of conductive pillars and the plurality of conductors; and

at least a second electronic element disposed on and electrically connected to the second circuit structure.

2 . The electronic package of claim 1 , further comprising a routing structure formed on the first side of the carrier structure and electrically connected to the plurality of conductive vias, wherein the first electronic element is disposed on and electrically connected to the routing structure.

3 . The electronic package of claim 1 , wherein the first electronic element is disposed on the carrier structure via a plurality of conductive bumps.

4 . The electronic package of claim 1 , wherein the surface of the first electronic element and end surfaces of the plurality of conductors are flush with the second surface of the encapsulation layer.

5 . The electronic package of claim 1 , wherein the plurality of conductive pillars have end surfaces flush with the second surface of the encapsulation layer.

6 . The electronic package of claim 1 , wherein the first circuit structure is free from being directly electrically connected to the first electronic element.

7 . The electronic package of claim 1 , wherein the second electronic element is disposed on the second circuit structure via a plurality of conductive bumps.

8 . The electronic package of claim 1 , wherein a plurality of the second electronic elements are disposed on the second circuit structure along a surface of the second circuit structure.

9 . The electronic package of claim 1 , further comprising a packaging layer covering the second electronic element.

10 . The electronic package of claim 1 , further comprising a plurality of conductive elements disposed on the first circuit structure.

11 . A method of manufacturing an electronic package, comprising:

providing an electronic module comprising a carrier structure and at least a first electronic element disposed on the carrier structure, wherein the first electronic element has a plurality of conductors penetrating through a surface of the first electronic element, wherein the carrier structure has a first side and a second side opposing the first side and a plurality of conductive vias communicating the first side and the second side, and wherein the first electronic element is disposed on the first side of the carrier structure and electrically connected to the plurality of conductive vias;

disposing the electronic module on a first circuit structure formed with a plurality of conductive pillars, wherein the first circuit structure is electrically connected to the plurality of conductive vias and the plurality of conductive pillars;

forming an encapsulation layer on the first circuit structure to cover the electronic module and the plurality of conductive pillars;

forming a second circuit structure on the encapsulation layer, wherein the second circuit structure is electrically connected to the plurality of conductive pillars and the plurality of conductors; and

disposing at least a second electronic element on the second circuit structure, wherein the second electronic element is electrically connected to the second circuit structure.

12 . The method of claim 11 , further comprising forming a routing structure on the first side of the carrier structure, the routing structure being electrically connected to the plurality of conductive vias, wherein the first electronic element is disposed on and electrically connected to the routing structure.

13 . The method of claim 11 , wherein the first electronic element is disposed on the carrier structure via a plurality of conductive bumps.

14 . The method of claim 11 , wherein the surface of the first electronic element and end surfaces of the plurality of conductors are flush with a surface of the encapsulation layer.

15 . The method of claim 11 , wherein the plurality of conductive pillars have end surfaces flush with a surface of the encapsulation layer.

16 . The method of claim 11 , wherein the first circuit structure is free from being directly electrically connected to the first electronic element.

17 . The method of claim 11 , wherein the second electronic element is disposed on the second circuit structure via a plurality of conductive bumps.

18 . The method of claim 11 , wherein a plurality of the second electronic elements are disposed on the second circuit structure along a surface of the second circuit structure.

19 . The method of claim 11 , further comprising covering the second electronic element by a packaging layer.

20 . The method of claim 11 , further comprising forming a plurality of conductive elements on the first circuit structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2022
From: KE, CHUNG-YU; CHEN, LIANG-PIN
To: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Reel/Frame 061567/0798 →
Priority Claims (1)
TW 111132958 · Aug 31, 2022 · national
Continuity (1)
Related Publication 20240072019A1 · Feb 29, 2024
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US 12,733,548