Gate structure for semiconductor device
The present disclosure describes semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate and a gate structure over the substrate, where the gate structure can include two opposing spacers, a dielectric layer formed on side surfaces of the two opposing spacers, and a gate metal stack formed over the dielectric layer. A top surface of the gate metal stack can be below a top surface of the dielectric layer. An example benefit of the semiconductor structure is to improve structure integrity of tight-pitch transistors in integrated circuits.
1 . A semiconductor structure, comprising:
a substrate;
a first source/drain region disposed on a first fin, on the substrate;
a second source/drain region disposed on a second fin on the substrate, wherein the first and second fins are parallel to each other;
a first plurality of stacked channels disposed on the first fin and adjacent to the first source/drain region;
a second plurality of stacked channels disposed on the second fin and adjacent to the second source/drain region;
a gate structure surrounding each of the plurality of stacked channels, the gate structure comprising:
two opposing spacers;
a dielectric layer disposed on side surfaces of the two opposing spacers; and
a gate metal stack disposed on the dielectric layer, wherein a top surface of the gate metal stack is below a top surface of the dielectric layer; and
an isolation structure comprising first and second isolation portions, wherein:
the first isolation portion is disposed between the first and second source/drain regions and vertically extends above top surfaces of the first and second plurality of stacked channels, and
the second isolation portion is disposed directly on the first isolation portion,
wherein the dielectric layer is disposed directly on a top surface of the second isolation portion and along sidewalls of the first and second isolation portions.
2 . The semiconductor structure of claim 1 , wherein the dielectric layer surrounds each of the plurality of stacked channels and is further disposed over top surfaces of the two opposing spacers.
3 . The semiconductor structure of claim 1 , wherein the top surface of the gate metal stack is below top surfaces of the two opposing spacers.
4 . The semiconductor structure of claim 1 , further comprising an isolation layer surrounded by the two opposing spacers, wherein the top surface of the dielectric layer is below a top surface of the isolation layer.
5 . The semiconductor structure of claim 1 , wherein sidewalls of the first and second isolation portions are non-adjacent to sidewalls of the first and second fins.
6 . A semiconductor structure, comprising:
a substrate;
a first source/drain region disposed on a first fin on the substrate;
a second source/drain region disposed on a second fin on the substrate, wherein the first and second fins are parallel to each other;
a first plurality of stacked channels disposed on the first fin and adjacent to the first source/drain region;
a second plurality of stacked channels disposed on the second fin and adjacent to the second source/drain region;
a gate structure comprising:
a first dielectric layer surrounding top and side surfaces of the plurality of stacked channels; and
a gate metal stack disposed on the first dielectric layer; and
an isolation structure comprising first and second isolation portions, wherein:
the first isolation portion is disposed between the first and second source/drain regions,
the second isolation portion is disposed directly on the first isolation portion and is surrounded by the gate structure,
a bottom surface of the second isolation portion is at a surface plane above top surfaces of the first and second plurality of stacked channels, and
a height of the second isolation portion is greater than a height of the first isolation portion,
wherein the first dielectric layer is disposed directly on a top surface of the second isolation portion and along sidewalls of the first and second isolation portions.
7 . The semiconductor structure of claim 6 , wherein a top surface of the gate metal stack is below a top surface of the second isolation portion.
8 . The semiconductor structure of claim 6 , further comprising two opposing spacers disposed on the plurality of stacked channels, wherein top surfaces of the two opposing spacers are above or substantially coplanar with a top surface of the second isolation portion.
9 . The semiconductor structure of claim 8 , wherein the first dielectric layer surrounds each of the plurality of stacked channels and is disposed on the top surfaces of the two opposing spacers, and
wherein the first dielectric layer comprises hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), hafnium aluminum oxide (HfAlO x ), or hafnium silicon oxide (HfSiO x ).
10 . The semiconductor structure of claim 6 , wherein the second isolation portion comprises a second dielectric layer and a third dielectric layer disposed on the second dielectric layer, and
wherein the second dielectric layer comprises a low-k dielectric material and the third dielectric layer comprises hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), hafnium aluminum oxide (HfAlO x ), hafnium silicon oxide (HfSiO x ), or a high-k dielectric material.
11 . The semiconductor structure of claim 6 , wherein the plurality of stacked channels comprise silicon and silicon-germanium.
12 . The semiconductor structure of claim 6 , wherein a top surface of the plurality of stacked channels is below a top surface of the second isolation portion.
13 . The semiconductor structure of claim 6 , wherein the second isolation portion comprises a high-k insulating block on top of a low-k dielectric stack.
14 . The semiconductor structure of claim 6 , further comprising:
a shallow trench isolation (STI) region disposed between the first and second fins and under the first isolation portion; and
an insulating liner disposed between a top surface of the STI region and a bottom surface of the first isolation portion.
15 . A device, comprising:
a substrate;
a first source/drain region disposed on a first fin on the substrate;
a second source/drain region disposed on a second fin on the substrate, wherein the first and second fins are parallel to each other;
an isolation structure, comprising:
a bottom isolation portion disposed between the first and second source/drain regions;
a top isolation portion disposed on the bottom isolation portion, wherein sidewalls of the top and bottom isolation portions are coplanar along a vertical plane;
a gate structure, comprising:
a metal gate;
a pair of opposing spacers; and
a dielectric layer interposed between the metal gate and the pair of opposing spacers and disposed directly on a top surface of the top isolation portion and along sidewalls of the top and bottom isolation portions.
16 . The device of claim 15 , further comprising nanostructured channels disposed on the first fin, wherein the dielectric layer surrounds each of the nanostructured channels and is on one or more of top and sidewall surfaces of the pair of opposing spacers.
17 . The device of claim 15 , wherein the dielectric layer is on sidewall surfaces and top surfaces of the opposing spacers, and the dielectric layer extends above the top surfaces of the pair of opposing spacers.
18 . The device of claim 15 , further comprising:
an interlayer dielectric (ILD) layer disposed on the isolation structure; and
a shallow trench isolation (STI) region disposed between the first and second fins and under the isolation structure.
19 . The device of claim 15 , further comprising a padding layer disposed on the metal gate and the pair of opposing spacers, wherein a top portion of the isolation structure is surrounded by the padding layer.
20 . The device of claim 15 , further comprising an insulating liner disposed under the bottom isolation portion, wherein the dielectric layer is disposed directly on sidewalls of the insulation liner.