Multi-least significant bit (LSB) dithering systems and methods
An electronic device may include an electronic display having multiple display pixels that display an image based on dithered image data. The electronic device may also include image processing circuitry that generates the dithered image data based on input image data and a threshold gray level that is greater than one. Generating the dithered image data may include replacing each gray level of the input image data that is less than the threshold gray level with either a zero gray level or the threshold gray level according to a dither pattern.
1 . An electronic device comprising:
an electronic display comprising a plurality of display pixels configured to display an image based on dithered image data; and
image processing circuitry configured to generate the dithered image data based on input image data and a threshold gray level, wherein generating the dithered image data comprises replacing each gray level of the input image data that is less than the threshold gray level with either a zero gray level or the threshold gray level according to a dither pattern, wherein the threshold gray level is greater than one, and wherein the threshold gray level is greater than a range of gray levels that cause display pixel non-uniformity when programmed into the plurality of display pixels.
2 . The electronic device of claim 1 , wherein replacing each gray level of the input image data that is less than the threshold gray level with either the zero gray level or the threshold gray level comprises:
determining whether the input image data comprises gray levels less than the threshold gray level; and
in response to determining that the input image data does comprise the gray levels less than the threshold gray level:
generating a low gray sub-image excluding gray levels above the threshold gray level;
dividing values of the low gray sub-image by the threshold gray level or an luminance value equivalent of the threshold gray level to generate fractional values; and
dithering the fractional values to generate a single dithered bit for each fractional value.
3 . The electronic device of claim 2 , wherein in response to determining that the input image data does comprise the gray levels less than the threshold gray level, the image processing circuitry is configured to:
degamma map the low gray sub-image from a gray level domain to a luminance domain to generate the values of the low gray sub-image; and
engamma map the single dithered bit for each fractional value from the luminance domain to the gray level domain.
4 . The electronic device of claim 2 , wherein in response to determining that the input image data does comprise the gray levels less than the threshold gray level, the image processing circuitry is configured to generate a processed low gray sub-image comprising the single dithered bit for each fractional value of the fractional values.
5 . The electronic device of claim 4 , wherein the image processing circuitry is configured to generate a high gray sub-image excluding the gray levels less than the threshold gray level.
6 . The electronic device of claim 5 , wherein the image processing circuitry is configured to dither gray values of the high gray sub-image from a first bit-depth to a second bit-depth, generating a processed high gray sub-image at the second bit-depth.
7 . The electronic device of claim 6 , wherein the image processing circuitry is configured to combine the processed high gray sub-image and the processed low gray sub-image to generate the dithered image data.
8 . The electronic device of claim 4 , wherein the single dithered bit for each fractional value is of the same order of magnitude of the threshold gray level.
9 . The electronic device of claim 2 , wherein the image processing circuitry is configured to truncate the fractional values to an N-bit-depth after the division, and wherein the dithering of the fractional values comprises dithering N−1 bits.
10 . The electronic device of claim 1 , wherein the image processing circuitry is configured to:
dither a high gray sub-image, wherein the high gray sub-image comprises gray level values greater than the threshold gray level and zero gray values in place of gray level values less than the threshold gray level;
dither a low gray sub-image, wherein the low gray sub-image comprises the gray level values less than the threshold gray level and the zero gray values in place of the gray level values greater than the threshold gray level; and
combine the dithered high gray sub-image and the dithered low gray sub-image to generate the dithered image data.
11 . A method comprising:
receiving, via a dither block of image processing circuitry, input image data;
determining whether a set of values of the input image data comprises values less than a threshold value; and
in response to determining that the input image data does comprise the values less the threshold value:
separating the set of values into a high gray sub-image and a low gray sub-image, wherein the high gray sub-image comprises values greater than the threshold value and the low gray sub-image comprises the values less than the threshold value;
dividing the values less than the threshold value of the low gray sub-image by the threshold value to generate fractional values;
dithering the fractional values to generate a single dithered bit for each fractional value; and
generating a processed low gray sub-image based on the single dithered bit for each fractional value; and
combine the processed low gray sub-image with the high gray sub-image or a processed high gray sub-image to generate dithered image data.
12 . The method of claim 11 , comprising degamma mapping the low gray sub-image and the threshold value prior to the division.
13 . The method of claim 12 , comprising engamma mapping the single dither bit for each fractional value prior to generating the processed low gray sub-image.
14 . The method of claim 11 , wherein the high gray sub-image comprises zero values in place of the values less than the threshold value, and wherein the low gray sub-image comprises the zero values in place of the values greater than the threshold value.
15 . The method of claim 11 , wherein the set of values are in a linear luminance domain.
16 . The method of claim 11 , comprising dithering the high gray sub-image by a number of bits to generate the processed high gray sub-image, wherein the processed high gray sub-image comprises a first bit-depth less than a second bit-depth of the high gray sub-image by the number of bits.
17 . The method of claim 11 , comprising determining the threshold value based on one or more characteristics of an electronic display coupled to the image processing circuitry.
18 . Image processing circuitry comprising:
least-significant-bit dither circuitry configured to dither a high gray sub-image, wherein the high gray sub-image comprises gray level values greater than a threshold gray level and zero gray values in place of gray level values less than the threshold gray level; and
multi-least-significant-bit dither circuitry configured to:
dither a low gray sub-image, wherein the low gray sub-image comprises the gray level values less than the threshold gray level and the zero gray values in place of the gray level values greater than the threshold gray level; and
combine the dithered high gray sub-image and the dithered low gray sub-image to generate dithered image data that does not include gray levels less than threshold gray level.
19 . The image processing circuitry of claim 18 , wherein the multi-least-significant-bit dither circuitry is configured to:
degamma map the gray levels less than the threshold gray level of the low gray sub-image to generate luminance values;
divide the luminance values by a threshold luminance value equivalent to the threshold gray level to generate fractional luminance values;
dither the fractional luminance values such that a bit-depth of the fractional luminance values is reduced to one; and
engamma map the dithered fractional luminance values to generate the dithered low gray sub-image.
20 . The image processing circuitry of claim 18 , wherein the threshold gray level is greater than gray level one.