Counter-based sense amplifier method for memory cells
Methods, systems, and devices for a counter-based sense amplifier method for memory cells are described. The described techniques provide for a memory system to store, in a counter associated with an array of memory cells, a value indicating a quantity of memory cells in the array having a predetermined logic value. The memory system may perform a read operation to read the data stored in the array of memory cells by applying a ramping bias voltage and may count the quantity of memory cells having the predetermined logic value during the read operation. The memory system may stop the read operation when the memory system identifies a quantity of memory cells having the predetermined logic value that is equal to the value stored to the counter.
1 . A memory system, comprising:
one or more arrays of memory cells;
one or more counters coupled with the one or more arrays of memory cells; and
one or more processors coupled with the one or more arrays of memory cells and configured to cause the memory system to:
store, at the one or more counters, a respective value corresponding to a quantity of respective memory cells of the one or more arrays of memory cells that store a first logic value;
read, from a counter of the one or more counters, a first value corresponding to the quantity of the respective memory cells storing the first logic value;
read, during a data reading phase, from the respective memory cells by applying a ramp of biasing voltages;
count, during the data reading phase, a quantity of bits of the respective memory cells having the first logic value; and
stop the data reading phase based at least in part on the quantity of bits having the first logic value.
2 . The memory system of claim 1 , wherein, to stop the data reading phase, the one or more processors are further configured to cause the memory system to:
stop the data reading phase based at least in part on the quantity of bits having the first logic value being greater than or equal to the first value stored at the counter.
3 . The memory system of claim 1 , wherein the one or more processors are further configured to cause the memory system to:
store one or more values to the one or more arrays of memory cells such that the quantity of bits having the first logic value is greater than or equal to half of the memory cells of the one or more arrays of memory cells.
4 . The memory system of claim 3 , wherein the one or more values are stored to the one or more arrays of memory cells during a programming phase, wherein the programming phase includes a Bit Flip phase to encode the one or more values corresponding to the first logic value and one or more values corresponding to a second logic value.
5 . The memory system of claim 1 , wherein to read the first value from the counter, the one or more processors are configured to perform a voltage ramp on the counter while starting a biasing pre-charge or line leakage compensation phase on the one or more arrays of memory cells.
6 . The memory system of claim 1 , wherein the one or more arrays of memory cells includes one or more codewords, each codeword of the one or more codewords comprising respective data bits with associated parity bits and a respective counter of the one or more counters with associated error correction bits.
7 . The memory system of claim 5 , wherein each codeword further comprises a group of Bit Flip cells with corresponding error correction bits.
8 . The memory system of claim 1 , wherein each cell of the one or more arrays of memory cells is configured to be turned off in response to being triggered.
9 . The memory system of claim 1 , wherein the one or more processors are further configured to cause the memory system to:
decrement the first value corresponding to the quantity of rhe respective memory cells that store the first logic value in response to a cell of the one or more arrays of memory cells being triggered.
10 . The memory system of claim 1 , wherein the first value is read from the counter and the respective memory cells are read using a voltage ramp having a same slope.
11 . The memory system of claim 1 , wherein a content of a last triggered cell of the one or more arrays of memory cells is stored to one or more latches for use in an error control operation.
12 . The memory system of claim 1 , wherein the data reading phase further comprises a try and repeat error control operation.
13 . The memory system of claim 12 , wherein the one or more processors are further configured to cause the memory system to:
initiate the try and repeat error control operation based at least in part on a quantity of triggered memory cells satisfying a threshold value.
14 . A memory device, comprising:
one or more memory arrays comprising one or more memory cells, the one or more memory arrays configured to store at least one codeword including data bits and parity bits;
one or more counters associated with error correction bits, the one or more counters storing a respective value corresponding to a quantity of respective memory cells of the one or more memory cells that store a first logic value; and
one or more processors supporting the memory device for reading the one or more memory cells.
15 . The memory device of claim 14 , wherein the at least one codeword comprises at least a group of Bit Flip cells with corresponding error correction bits.
16 . The memory device of claim 15 , wherein the group of Bit Flip cells includes a quantity from 1 to N of cells based at least in part on the at least one codeword.
17 . The memory device of claim 14 , wherein the one or more memory cells comprise one or more three-dimensional cross point memory cells.
18 . The memory device of claim 14 , wherein the memory device further comprises:
one or more latches associated with a respective sense amplifier and configured to store a content of a last triggered cell of the one or more memory cells for use in soft error correction techniques.
19 . The memory device of claim 14 , wherein the one or more processors are configured to perform a counter reading phase in parallel with a biasing pre-charge or line leakage compensation phase of the data bits.
20 . A memory device, comprising:
one or more arrays of memory cells;
one or more counters associated with a respective codeword of the one or more arrays and coupled with the one or more arrays of memory cells; and
one or more processors coupled with the one or more arrays of memory cells and configured to cause the memory device to:
store, at the one or more counters, a value of a number of bits of the respective codeword having a first logic value;
start a counter reading phase, prior to starting a codeword reading phase, during a pre-charge phase to read a content of the one or more counters; and
stop the codeword reading phase when the number of bits having the first logic value is greater than or equal to the content of the one or more counters.