IP Library › Granted Patent US 12,500,116
Granted Patent B2
US 12,500,116 · App. 17/577,194 · Granted Dec 16, 2025

Method for making deep trench isolation of CIS device, and semiconductor device structure

Inventors: Jialong Li (Wuxi, CN); Peng Huang (Wuxi, CN); Xiao Fan (Wuxi, CN); Wensheng Qian (Wuxi, CN)
Assignee: Hua Hong Semiconductor (Wuxi) Limited
H01L21/76224H01L21/76202H10F39/014H10F39/807
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,500,116
App. No.
17/577,194
Granted
Dec 16, 2025
Kind
B2
Abstract

A method for making a deep trench isolation of a CIS device includes: growing a first epitaxial layer on a substrate; forming a hard mask layer on the first epitaxial layer; performing photolithography and etching processes to form deep trenches arranged longitudinally and transversely in the first epitaxial layer; forming a second epitaxial layer in the deep trenches; performing a thermal oxidation process to form a first oxide layer on the surface of the second epitaxial layer; completely filling the deep trenches with polysilicon; performing a back-etching process to expose sidewalls of the first oxide layer in the deep trenches; forming a second oxide layer on the top of the polysilicon; removing the hard mask layer and the first oxide layer above the second oxide layer; rapidly growing a third epitaxial layer; and performing a CMP process to form a deep trench isolation on the substrate.

Claims (19)

1 . A method for making a deep trench isolation of a CIS device, comprising:

growing a first epitaxial layer on a substrate, and the conductive type of the first epitaxial layer being N type;

forming a hard mask layer on the surface of the first epitaxial layer;

performing photolithography and etching processes to form deep trenches arranged longitudinally and transversely in the first epitaxial layer;

forming a second epitaxial layer in the deep trenches, sidewalls and bottoms of the deep trenches being completely covered by the second epitaxial layer, and the conductive type of the second epitaxial layer being P type;

performing a thermal oxidation process to form a first oxide layer with a predetermined thickness on the surface of the second epitaxial layer in the deep trenches;

completely filling the deep trenches with a polysilicon;

performing a back-etching process to the substrate to expose sidewalls of the first oxide layer in the deep trenches;

forming a second oxide layer on the top of the polysilicon in the deep trenches;

removing the hard mask layer on the surface of the substrate and the first oxide layer above the second oxide layer;

rapidly growing a third epitaxial layer, the third epitaxial layer covering tops of the deep trenches, and the conductive type of the third epitaxial layer being P type; and

performing a CMP process to form a deep trench isolation on the substrate.

2 . The method for making a deep trench isolation of a CIS device, according to claim 1 , wherein the doping concentration of the third epitaxial layer is higher than the doping concentration of the second epitaxial layer.

3 . The method for making a deep trench isolation of a CIS device, according to claim 1 , wherein forming the second epitaxial layer in the deep trenches comprises:

performing a doped epitaxial growth process to grow a second epitaxial layer on the sidewalls and bottoms of the deep trenches.

4 . The method for making a deep trench isolation of a CIS device, according to claim 1 , wherein removing the hard mask layer on the surface of the substrate and the first oxide layer above the second oxide layer comprises:

performing wet etching processes to removing the hard mask layer on the surface of the substrate and the first oxide layer higher than the second oxide layer in the deep trenches.

5 . The method for making a deep trench isolation of a CIS device, according to claim 1 , wherein the material of the hard mask layer is silicon nitride or silicon dioxide.

6 . The method for making a deep trench isolation of a CIS device, according to claim 1 , wherein the polysilicon filled in the deep trenches is doped polysilicon.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2022
From: LI, JIALONG; HUANG, PENG; FAN, XIAO; QIAN, WENSHENG
To: HUA HONG SEMICONDUCTOR (WUXI) LIMITED; SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 058752/0031 →
Priority Claims (1)
CN 202110075783.X · Jan 20, 2021 · national
Continuity (1)
Related Publication 20220230909A1 · Jul 21, 2022
References Cited (2)
US 11049957B1 · Yoo · 2021 [cited by examiner]
US 20160163749A1 · Yang · 2016 [cited by examiner]