Granted Patent B2

US 12,500,203 · App. 17/676,700 · Granted Dec 16, 2025

Inventor: Weiping Li (Shanghai, CN)

Assignee: Yibu Semiconductor Co., Ltd.

H01L24/81H01L21/56H01L23/485H01L25/105H01L25/50H01L2224/81143H01L2224/81203

Abstract

Claims (40)

1 . A semiconductor packaging method, comprising:

forming a first-level assembly, including:

providing at least one first-level device, at least one second-level device, and a carrier board, wherein the at least one first-level device has at least one first-level first surface formed with first-level interconnect terminals and at least one opposing first-level second surface formed with first-level first alignment solder parts, the at least one second-level device has at least one second-level first surface formed with second-level interconnect terminals and second-level first alignment solder parts, and the carrier board is formed with first-level second alignment solder parts respectively corresponding to the first-level first alignment solder parts;

placing the at least one first-level device on the carrier board such that the first alignment solder parts are substantially aligned with respective ones of the second alignment solder parts;

forming first-level alignment solder joints by soldering the first-level first alignment solder parts to respective ones of the first-level second alignment solder parts to align and fix the at least one first-level device to one side of the carrier board;

encapsulating the at least one first-level device on the side of the carrier board in a molding compound to form a molded package body on the side of the carrier board;

exposing the first-level interconnect terminals from the molded package body;

sequentially forming an interconnect layer and interposer terminals corresponding to the second-level interconnect terminals on a side of the molded package body where the first-level interconnect terminals are exposed such that at least some of the first-level interconnect terminals are respectively electrically connected to the interposer terminals, through the interconnect layer; and

forming second-level second alignment solder parts corresponding to the second-level first alignment solder parts, respectively, on the interconnect layer;

placing the at least one second-level device over the first-level assembly such that the second-level first alignment solder parts are substantially aligned with the second-level second alignment solder parts;

forming second-level alignment solder joints by soldering the second-level first alignment solder parts and the second-level second alignment solder parts so that the at least one second-level device is aligned to the first-level assembly;

pressing the at least one second-level device and the first-level assembly toward each other while the second-level alignment solder joints are at least partially melted to respectively join the second-level interconnect terminals and the interposer terminals to form interconnect joints; and

releasing the pressing.

2 . The semiconductor packaging method according to claim 1 , wherein the at least one first-level device and the at least one second-level device includes at least one of a semiconductor device and an interconnect board, the interconnect board being an interposer or a substrate.

3 . The semiconductor packaging method according to claim 1 , wherein at least one of the at least one first-level device and the at least one second-level device further includes a through electrode.

4 . The semiconductor packaging method according to claim 1 , wherein a sum of heights of a second-level interconnect terminal and a corresponding interposer terminal is less than a sum of heights of a second-level first alignment solder part and a corresponding second-level second alignment solder part, such that the second-level interconnect terminals are spaced apart from the interposer terminals after the second-level first alignment solder parts and the second-level second alignment solder parts form second-level alignment solder joints.

5 . The semiconductor packaging method according to claim 1 , further comprising forming external interconnect terminals on the interconnect layer, wherein at least some of the first-level interconnect terminals and interposer terminals are respectively electrically connected to the external interconnect terminals through the interconnect layer.

6 . The semiconductor packaging method according to claim 1 , wherein:

respectively joining the second-level interconnect terminals and the interposer terminals to form interconnect joints includes, while the at least one second-level device is in alignment with the first-level assembly and the second-level alignment solder joints are in an at least partially molten state, pressing the at least one second-level device and the first-level assembly toward each other; or

respectively joining the second-level interconnect terminals and the interposer terminals to form interconnect joints includes, after the at least one second-level device is in alignment with the first-level assembly, applying heat to melt the second-level alignment solder joints again and pressing the at least one second-level device and the first-level assembly toward each other while the second-level alignment solder joints are in a molten or partially molten state.

7 . The semiconductor packaging method according to claim 6 , wherein the external interconnect terminals are spaced apart from the second level second alignment solder parts so as not to be covered by a perpendicular projection of the at least one second-level device on the interconnect layer after the at least one second-level device is aligned with the first-level assembly.

8 . The semiconductor packaging method according to claim 1 , wherein:

the second-level interconnect terminals are interconnect bumps, and the interposer terminals are interposer bumps or interposer pads; or

the second-level interconnect terminals are interconnect pads and the interposer terminals are interposer bumps.

9 . The semiconductor packaging method according to claim 8 , wherein:

the interconnect bumps are solder bumps and respectively joining the second-level interconnect terminals and the interposer terminals includes soldering the second-level interconnect terminals to respective ones of the interposer terminals to form interconnect joints; or

the interconnect bumps do not include solder and respectively joining the second-level interconnect terminals and the interposer terminals includes bonding the second-level interconnect terminals and respective ones of the interposer terminals by thermocompression bonding.

10 . A semiconductor component packaged using the semiconductor packaging method of claim 1 .

11 . A semiconductor packaging method, comprising:

forming a first-level assembly, including:

providing at least one first-level device, at least one second-level device, and a carrier board, wherein the at least one first-level device has at least one first-level first surface formed with first-level interconnect bumps and at least one opposing first-level second surface formed with first-level first alignment solder parts, the at least one second-level device has at least one second-level first surface formed with second-level interconnect bumps and second-level first alignment solder parts, and the carrier board is formed with first-level second alignment solder parts respectively corresponding to the first-level first alignment solder parts;

placing the at least one first-level device on the carrier board such that the first-level first alignment solder parts are substantially aligned with respective ones of the first-level second alignment solder parts;

forming first-level alignment solder joints by soldering the first alignment solder parts to respective ones of the second alignment solder parts to align and fix the at least one first-level device to one side of the carrier board;

encapsulating the at least one first-level device on the side of the carrier board in a molding compound to form a molded package body on the side of the carrier board; and

exposing the first-level interconnect bumps from the molded package body;

placing the at least one second-level device over the first-level assembly such that the second-level first alignment solder parts are substantially aligned with second-level second alignment solder parts on the first-level assembly;

forming second-level alignment solder joints by soldering the second-level first alignment solder parts and the second-level second alignment solder parts so that the at least one second-level device is aligned to the first-level assembly;

pressing the at least one second-level device and the first-level assembly toward each other while the second-level alignment solder joints are at least partially melted to respectively join the second-level interconnect bumps and corresponding ones of the first-level interconnect bumps to form interconnect joints; and

releasing the pressing;

wherein a height of each second-level interconnect bump is less than a height of each second-level first alignment solder part, such that the second-level interconnect bumps are spaced apart from corresponding first-level interconnect bumps after the second-level first alignment solder parts and the second-level second alignment solder parts form second-level alignment solder joints.

Assignments (1)

Priority Claims (1)

Continuity (3)

References Cited (103)