Semiconductor device and manufacturing method thereof
View Patent ↗In a method of manufacturing a semiconductor device, a fin structure having a bottom part and an upper part on the bottom part is formed over a substrate. The bottom part is trimmed so that a width of an uppermost portion of the bottom part is smaller than a width of the upper part. Bottom end corners of the upper part are trimmed to reduce a width of the upper part at a bottom of the upper part. An isolation insulating layer is formed so that the upper part protrudes from the isolation insulating layer. A dummy gate structure is formed. A source/drain structure is formed. An interlayer dielectric layer is formed over the dummy gate structure and the source/drain structure. The dummy gate structure is replaced with a metal gate structure.
1 . A semiconductor device, comprising:
an isolation insulating layer disposed on a substrate;
a fin structure having a lower part and an upper part protruding from the substrate;
a source/drain structure, wherein:
the upper part includes a bottom portion and a top portion disposed on the bottom portion, the upper portion has a tapered shape, and the bottom portion has a reverse tapered shape so that an uppermost portion of the upper part has a width less than a lowermost portion of the upper part,
the lower part has the tapered shape,
a neck portion located between the upper part and the lower part, which is located below a portion having a largest width of the upper part, is covered by a gate dielectric layer, and
the upper part of the fin structure is made of a different semiconductor material than the lower part of the fin structure.
2 . The semiconductor device of claim 1 , wherein the upper part of the fin structure is made of SiGe and the lower part of the fin structure is made of Si.
3 . The semiconductor device of claim 1 , wherein a top portion of the lower part of the fin structure is covered by the gate dielectric layer.
4 . The semiconductor device of claim 1 , wherein the gate dielectric layer is in contact with the isolation insulating layer.
5 . The semiconductor device of claim 1 , wherein an upper surface of the isolation insulating layer is located below an interface between the lower part and the upper part of the fin structure, and a height of the upper surface of the isolation insulating layer measured from the interface is from 0% to 20% of a vertical length of the upper part of the fin structure.
6 . The semiconductor device of claim 5 , wherein the vertical length of the upper part is in a range from 30 nm to 70 nm.
7 . The semiconductor device of claim 1 , wherein a width of the lower part at an interface between the lower part and the upper part of the fin structure is 50% to 95% of an average width of the upper part.
8 . The semiconductor device of claim 1 , wherein the source/drain structure includes a source/drain fin structure and a source/drain epitaxial layer, and a bottom of the source/drain epitaxial layer is within +10 nm of an interface between the lower part and the upper part of the fin structure.
9 . The semiconductor device of claim 1 , wherein some portions of the lower part of the fin structure are partially covered by the isolation insulating layer.
10 . The semiconductor device of claim 1 , wherein one or more fin liner layers are formed between the isolation insulating layer and the substrate.
11 . The semiconductor device of claim 1 , an entirety of the upper part of the fin structure is covered by the gate dielectric layer.
12 . A semiconductor device, comprising:
an isolation insulating layer disposed on a substrate;
a first fin structure and a second fin structure, each having a lower part and an upper part disposed on the substrate, the upper part protruding from the substrate and including a bottom portion and an upper portion disposed on the bottom portion;
a gate structure disposed on and covering the upper part of each of the first and second fin structures;
a source/drain structure including a source/drain epitaxial layer, wherein:
the upper portion of the upper part has a tapered shape, and the bottom portion of the upper part has a reverse tapered shape so that an uppermost portion of the upper part has a width less than a lowermost portion of the upper part,
an entirety of the lower part has the tapered shape,
a largest width of the upper part of each of the first and second fin structures is located at a level above an interface between the upper part and the lower part,
a neck portion located between the upper part and the lower part, which is located below a portion having a largest width of the upper part, is covered by a gate dielectric layer, and
the gate dielectric layer is in contact with the isolation insulating layer.
13 . The semiconductor device of claim 12 , wherein the bottom portion and the upper portion are continuous and made of a same material.
14 . The semiconductor device of claim 12 , wherein the upper part of the fin structure is made of a different semiconductor material than the lower part of the fin structure.
15 . The semiconductor device of claim 12 , wherein a height of an upper surface of the isolation insulating layer measured from an interface between the lower part and the upper part of the fin structure is within 0% to 20% of a vertical length of the upper part of the fin structure, and the vertical length of the upper part is in a range from 30 nm to 70 nm.
16 . The semiconductor device of claim 12 , wherein some portions of the lower part of the fin structure are partially covered by the isolation insulating layer.
17 . The semiconductor device of claim 12 , wherein the gate structure partially covers a top portion of the bottom part of the fin structure.
18 . The semiconductor device of claim 12 , wherein the upper part of the fin structure is made of SiGe and the lower part of the fin structure is made of Si.
19 . A method of manufacturing a semiconductor device, the method comprising:
forming a semiconductor layer over a semiconductor substrate;
forming a fin structure by patterning the semiconductor layer and the semiconductor substrate using a dielectric hard mask pattern, so that the fin structure has a lower part corresponding to the semiconductor substrate and an upper part corresponding to the semiconductor layer;
trimming the lower part so that a width of the lower part is smaller than a width of the upper part;
trimming bottom end corners of the upper part to reduce a width of a bottom of the upper part; and
after the trimming the bottom end corners, forming an isolation insulating layer so that the lower part of the fin structure is partially covered by the isolation insulating layer, wherein:
the upper part includes a bottom portion and a top portion disposed on the bottom portion, the upper portion has a tapered shape, and the bottom portion has a reverse tapered shape so that an uppermost portion of the upper part has a width less than a lowermost portion of the upper part, and
the lower part has the tapered shape.
20 . The method of claim 19 , wherein the semiconductor layer is made of a different semiconductor material than the semiconductor substrate.