Memory cell and method of operating the same
A memory cell includes a read word line extending in a first direction, a write transistor, and a read transistor coupled to the write transistor. The read transistor includes a ferroelectric layer, a drain terminal of the read transistor directly connected to the read word line, and a source terminal of the read transistor coupled to a first node. The write transistor is configured to adjust a polarization state of the read transistor, the polarization state corresponding to a stored data value of the memory cell.
1 . A memory cell, comprising:
a read word line extending in a first direction;
a write transistor
a read transistor coupled to the write transistor, the read transistor comprising:
a ferroelectric layer;
a drain terminal of the read transistor directly connected to the read word line; and
a source terminal of the read transistor coupled to a first node;
wherein the write transistor is configured to adjust a polarization state of the read transistor, the polarization state corresponding to a stored data value of the memory cell, and during a read operation of the memory cell, adjusting a voltage of the read word line from a first read voltage to a second read voltage different from the first read voltage.
2 . The memory cell of claim 1 , wherein the ferroelectric layer includes a ferroelectric material including HfO 2 , HfZrO, HfO or combinations thereof.
3 . The memory cell of claim 1 , wherein the write transistor comprises:
a drain terminal of the write transistor coupled to a write bit line;
a source terminal of the write transistor coupled to the read transistor; and
a gate terminal of the write transistor coupled to a write word line.
4 . The memory cell of claim 3 , wherein the read transistor further comprises:
a gate terminal of the read transistor coupled to the source terminal of the write transistor, and the gate terminal of the read transistor is on a surface of the ferroelectric layer.
5 . The memory cell of claim 4 , further comprising:
a read bit line;
a first transistor coupled between the read bit line and the read transistor, the first transistor comprising:
a drain terminal of the first transistor coupled to the source terminal of the read transistor by the first node;
a source terminal of the first transistor coupled to the read bit line; and
a gate terminal of the first transistor.
6 . The memory cell of claim 5 , wherein the gate terminal of the first transistor is configured to receive a control signal.
7 . The memory cell of claim 4 , further comprising:
a read bit line,
wherein the source terminal of the read transistor is directly connected to the read bit line by a second node.
8 . A memory cell, comprising:
a write word line extending in a first direction, and configured to supply a write word line signal;
a read word line extending in the first direction, and being separated from the write word line in a second direction different from the first direction;
a write transistor of a first transistor type, coupled to the write word line, the write transistor configured to be enabled or disabled in response to the write word line signal; and
a read transistor of the first transistor type coupled to the write transistor, the read transistor comprising:
a drain terminal of the read transistor is directly connected to the read word line;
a gate terminal of the read transistor coupled to the write transistor; and
a ferroelectric layer having a polarization state that corresponds to a stored data value in the memory cell;
wherein the write transistor is configured to adjust the polarization state of the ferroelectric layer, and during a read operation of the memory cell, adjusting a voltage of the read word line from a first read voltage to a second read voltage different from the first read voltage.
9 . The memory cell of claim 8 , wherein the ferroelectric layer includes a ferroelectric material including HfO 2 , HfZrO, HfO or combinations thereof.
10 . The memory cell of claim 8 , wherein the read transistor further comprises:
a channel region;
a gate insulating layer above the channel region; and
a gate layer above the ferroelectric layer,
wherein the ferroelectric layer is between the gate insulating layer and the gate layer.
11 . The memory cell of claim 8 , wherein
the write transistor includes a first oxide channel region; and
the read transistor includes a second oxide channel region.
12 . The memory cell of claim 8 , wherein
the write transistor includes an oxide channel region; and
the read transistor includes a silicon channel region.
13 . The memory cell of claim 8 , wherein the read transistor further comprises:
a source terminal of the read transistor coupled to a first node.
14 . The memory cell of claim 13 , further comprising:
a read bit line; and
a first transistor of the first transistor type, the first transistor being coupled between the read transistor and the read bit line, the first transistor comprising:
a drain terminal of the first transistor coupled to the source terminal of the read transistor by the first node;
a source terminal of the first transistor coupled to the read bit line; and
a gate terminal of the first transistor configured to receive a control signal.
15 . The memory cell of claim 13 , further comprising:
a read bit line,
wherein the source terminal of the read transistor is coupled to the read bit line by the first node.
16 . A method of operating a memory cell, the method comprising:
performing a read operation of the memory cell, the performing the read operation of the memory cell comprising:
pre-discharging a voltage of a read bit line to a first voltage or pre-charging the voltage of the read bit line to a second voltage different from the first voltage;
adjusting a voltage of a read word line from a third voltage to a fourth voltage, the read word line being directly connected to a drain of a read transistor; and
sensing the voltage of the read bit line in response to adjusting the voltage of the read word line from the third voltage to the fourth voltage thereby outputting a stored data value in the memory cell.
17 . The method of claim 16 , further comprising:
performing a write operation of the memory cell.
18 . The method of claim 16 , wherein the stored data value of the memory cell has a first logical value corresponding to a first resistance state of the read transistor, or a second logical value corresponding to a second resistance state of the read transistor, the second logical value being opposite of the first logical value, the second resistance state being opposite of the first resistance state.
19 . The method of claim 16 , wherein the third voltage is a voltage of a logically high signal, and the fourth voltage is a voltage of a logically low signal.
20 . The method of claim 16 , wherein adjusting the voltage of the read word line from the third voltage to the fourth voltage comprises:
turning on a first transistor in response to a first control signal or the voltage of the read word line being the fourth voltage thereby electrically coupling the read bit line to a source of the read transistor.