Vertical memory devices and methods of manufacturing the same
A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.
1 . A vertical memory device, comprising:
a gate electrode structure including gate electrodes that are spaced apart from each other and stacked in a staircase shape on a substrate in a first direction substantially perpendicular to an upper surface of the substrate, the gate electrode structure including a first gate electrode and second gate electrodes under the first gate electrode;
a channel extending through the gate electrode structure in the first direction; and
a contact plug including:
a first extension portion extending in the first direction, the first extension portion penetrating through but being insulated from the second gate electrodes; and
a second extension portion contacting a sidewall of the first extension portion and a sidewall of the first gate electrode.
2 . The vertical memory device of claim 1 , further comprising an insulation pattern between the second extension portion of the contact plug and each of the second gate electrodes.
3 . The vertical memory device of claim 1 , wherein an upper surface of the first extension portion of the contact plug is higher than an upper surface of the first gate electrode.
4 . The vertical memory device of claim 1 , further comprising:
a circuit pattern on the substrate;
an insulating interlayer on the substrate, the insulating interlayer covering the circuit pattern; and
a base pattern on the insulating interlayer,
wherein the gate electrode structure and the channel are disposed on the base pattern, and
wherein the contact plug at least partially extends through the insulating interlayer, and is electrically connected to the circuit pattern.
5 . The vertical memory device of claim 4 , wherein the base pattern includes silicon.
6 . The vertical memory device of claim 4 , wherein the substrate includes:
a cell array region at a central portion of the substrate in a second direction substantially parallel to the upper surface of the substrate; and
a pad region at each of edge portions of the substrate in the second direction, and
wherein the channel and the base pattern are disposed on the cell array region of the substrate, and pads of the gate electrodes and the contact plug are disposed on the pad region of the substrate.
7 . The vertical memory device of claim 6 , wherein the base pattern is disposed only on the cell array region of the substrate.
8 . A vertical memory device, comprising:
a gate electrode structure including gate electrodes that are spaced apart from each other and stacked in a staircase shape on a substrate in a first direction substantially perpendicular to an upper surface of the substrate;
a channel extending through the gate electrode structure in the first direction; and
a contact plug contacting a first gate electrode among the gate electrodes and extending through but electrically insulated from second gate electrodes among the gate electrodes,
wherein the contact plug includes:
a first extension portion extending in the first direction; and
a second extension portion connected to the first extension portion, the second extension portion extending in a second direction substantially parallel to the upper surface of the substrate, and
wherein a thickness of the second extension portion of the contact plug in the first direction is greater than a thickness of the first gate electrode in the first direction.
9 . The vertical memory device of claim 8 , wherein the second gate electrodes are disposed under the first gate electrode, and
wherein the second extension portion of the contact plug contacts the first gate electrode.
10 . The vertical memory device of claim 8 , further comprising an insulation pattern between the second extension portion of the contact plug and each of the second gate electrodes.
11 . The vertical memory device of claim 8 , wherein an upper surface of the first extension portion of the contact plug is higher than an upper surface of the first gate electrode.
12 . The vertical memory device of claim 8 , further comprising:
a circuit pattern on the substrate;
an insulating interlayer on the substrate, the insulating interlayer covering the circuit pattern; and
a base pattern on the insulating interlayer,
wherein the gate electrodes and the channel are disposed on the base pattern, and
wherein the contact plug at least partially extends through the insulating interlayer, and is electrically connected to the circuit pattern.
13 . The vertical memory device of claim 12 , wherein the base pattern includes silicon.
14 . The vertical memory device of claim 12 , wherein the substrate includes:
a cell array region at a central portion of the substrate in a second direction substantially parallel to the upper surface of the substrate; and
a pad region at each of edge portions of the substrate in the second direction, and
wherein the channel and the base pattern are disposed on the cell array region of the substrate, and pads of the gate electrodes and the contact plug are disposed on the pad region of the substrate.
15 . The vertical memory device of claim 14 , wherein the base pattern is disposed only on the cell array region of the substrate.
16 . A vertical memory device, comprising:
a gate electrode structure including gate electrodes that are spaced apart from each other and stacked in a staircase shape in a first direction substantially perpendicular to an upper surface of a substrate;
a channel extending through the gate electrode structure in the first direction; and
a contact plug contacting a first gate electrode among the gate electrodes and extending through but electrically insulated from second gate electrodes among the gate electrodes,
wherein the contact plug includes:
a first extension portion extending in the first direction; and
a second extension portion contacting a sidewall of the first extension portion and a sidewall of the first gate electrode, the second extension portion extending in a second direction substantially parallel to the upper surface of the substrate, and
wherein a first distance from the sidewall of the first extension portion of the contact plug to the sidewall of the first gate electrode contacting the second extension portion of the contact plug is different from a second distance from the sidewall of the first extension portion of the contact plug to a sidewall of each of the second gate electrodes facing the first extension portion of the contact plug.
17 . The vertical memory device of claim 16 , wherein the first distance is greater than the second distance.
18 . The vertical memory device of claim 16 , wherein the second gate electrodes are disposed under the first gate electrode.
19 . The vertical memory device of claim 16 , further comprising an insulation pattern between the second extension portion of the contact plug and each of the second gate electrodes.
20 . The vertical memory device of claim 16 , wherein an upper surface of the first extension portion of the contact plug is higher than an upper surface of the first gate electrode.