Measurement instrument having time, frequency and logic domain channels
A measurement apparatus is provided for measuring signals from a device under test (DUT). The measurement apparatus includes a time domain receiver configured to receive from the DUT a time domain signal in a time domain; a logic domain receiver configured to receive from the DUT a logical signal comprising logic levels over time; a frequency domain receiver configured to receive from the DUT a frequency domain signal in a frequency domain through frequency downconversion; and a controller coupled to the logic domain receiver, and configured to determine the logic levels over time of the logical signal and to control at least one parameter of the frequency domain signal in response to the determined logic levels.
1 . A measurement apparatus for measuring signals from a device under test (DUT), the measurement apparatus comprising:
a time domain receiver configured to receive from the DUT a DUT time domain output signal in a time domain and to provide a time domain input signal;
a logic domain receiver configured to receive from the DUT a DUT logic domain output signal comprising logic levels over time;
a frequency domain receiver configured to receive from the DUT a DUT frequency domain output signal in a frequency domain and to provide a frequency domain input signal; and
a controller coupled to the logic domain receiver, and configured to determine control signals in response to the logic levels from the DUT logic domain output signal for controlling at least one parameter of the frequency domain input signal.
2 . The measurement apparatus of claim 1 , wherein the at least one parameter controlled by the controller includes an acquisition frequency.
3 . The measurement apparatus of claim 1 , wherein the at least one parameter controlled by the controller includes an amplitude of the frequency domain input signal.
4 . The measurement apparatus of claim 1 , wherein the controller includes processor and a memory storing instructions that, when executed, cause the processor to control, based on the logic levels, the at least one parameter of the frequency domain input signal.
5 . The measurement apparatus of claim 1 , wherein the logic domain receiver comprises a one-bit quantizer configured to interpret the DUT logic domain output signal to be a logic zero when below a threshold and a logic one when above the threshold.
6 . The measurement apparatus of claim 1 , wherein the DUT frequency domain output signal comprises a hopped frequency domain signal.
7 . The measurement apparatus of claim 6 , wherein the logic levels comprise a frequency control word (FCW) representing a center frequency of the hopped frequency domain signal.
8 . The measurement apparatus of claim 7 , further comprising:
a local oscillator (LO) configured to generate a LO signal, and to provide the LO signal to an external mixer, outside the measurement apparatus, for mixing the LO signal and the DUT frequency domain output signal to provide a frequency downconverted frequency domain signal to the frequency domain receiver.
9 . A measurement apparatus for measuring signals from a device under test (DUT), the measurement apparatus comprising:
a time domain receiver configured to receive a DUT time domain output signal from the DUT in a time domain and to provide a time domain input signal;
a logic domain receiver configured to receive a DUT logic domain output signal from the DUT comprising logic levels over time;
a local oscillator (LO) configured to generate a LO signal, and to provide the LO signal to a mixer configured to mix the LO signal and a hopped DUT frequency domain output signal from the DUT to provide a downconverted frequency domain signal;
a frequency domain receiver configured to receive the downconverted frequency signal in a frequency domain and to provide a frequency domain input signal; and
a controller coupled to the logic domain receiver, and configured to determine control signals in response to the logic levels for controlling at least one parameter of the frequency domain input signal,
wherein the logic levels comprise a frequency control word (FCW) representing a center frequency of the hopped DUT frequency domain output signal, and
wherein the controller is further configured to synchronously adjust timing and frequency parameters of the LO to match timing and corresponding frequency parameters of the hopped DUT frequency domain output signal.
10 . The measurement apparatus of claim 9 , wherein the controller includes processor and a memory storing instructions that, when executed, cause the processor to control, based on the logic levels, the at least one parameter of the frequency domain input signal.
11 . The measurement apparatus of claim 9 , wherein the logic domain receiver comprises a one-bit quantizer configured to interpret the DUT logic domain output signal to be a logic zero when below a threshold and a logic one when above the threshold.