Memory device and method for computing-in-memory (CIM)
View Patent ↗A memory device has a memory array including a memory segment to store weight data, a weight buffer coupled to the memory segment and configured to hold new weight data to be updated in the memory segment, a logic circuit, and a computation circuit coupled to an output of the logic circuit. The logic circuit further has a first input coupled to the memory segment by a bit line, and a second input configured to receive input data. The logic circuit is configured to generate, at the output, intermediate data corresponding to the input data and the weight data read from the memory segment through the bit line. The computation circuit is configured to, based on the intermediate data, generate output data corresponding to a computation performed on the input data and the weight data read from the at least one memory segment.
1 . A memory device, comprising:
a memory array comprising at least one memory segment configured to store weight data;
at least one weight buffer coupled to the at least one memory segment, and configured to hold new weight data to be updated in the at least one memory segment;
at least one logic circuit having
a first input coupled to the at least one memory segment by at least one bit line,
a second input configured to receive input data, and
an output; and
a computation circuit coupled to the output of the at least one logic circuit,
wherein
the at least one logic circuit is configured to generate, at the output, intermediate data corresponding to the input data and the weight data read from the at least one memory segment through the at least one bit line, and
the computation circuit is configured to, based on the intermediate data, generate output data corresponding to a computation performed on the input data and the weight data read from the at least one memory segment.
2 . The memory device of claim 1 , wherein
the memory array, the at least one weight buffer, the at least one logic circuit and the computation circuit are included in a same memory macro.
3 . The memory device of claim 1 , wherein
the at least one logic circuit comprises a NOR gate or an AND gate.
4 . The memory device of claim 1 , wherein
the computation circuit comprises a Multiply Accumulate (MAC) circuit.
5 . The memory device of claim 4 , wherein
the MAC circuit comprises an adder tree having a plurality of adder stages.
6 . The memory device of claim 1 , further comprising:
at least one register coupled to the at least one bit line, between the at least one memory segment and the first input of the at least one logic circuit.
7 . The memory device of claim 6 , wherein
the at least one memory segment comprises single-port memory cells coupled to the at least one bit line.
8 . The memory device of claim 1 , wherein
the at least one memory segment comprises a plurality of memory cells each having
a storage circuit configured to store a corresponding piece of the weight data, and
an output buffer coupled between the storage circuit and the at least one bit line.
9 . The memory device of claim 8 , wherein
the output buffer comprises an inverter and a transmission gate,
the inverter is coupled between the storage circuit and the transmission gate, and
the transmission gate is coupled between the inverter and the at least one bit line.
10 . The memory device of claim 8 , wherein
the at least one bit line comprises a first bit line and a second bit line,
each of the plurality of memory cells is a multiport memory cell having
a first read port coupled to the first bit line, and
a second read port coupled to the second bit line, and
the at least one logic circuit comprises
a first logic circuit having a first input coupled to the first bit line, and a second input configured to receive a first part of the input data, and
a second logic circuit having a first input coupled to the second bit line, and a second input configured to receive a second part of the input data.
11 . The memory device of claim 10 , further comprising:
a first register coupled to the first bit line, between the at least one memory segment and the first logic circuit; and
a second register coupled to the second bit line, between the at least one memory segment and the second logic circuit.
12 . A memory device comprising:
a memory segment;
a weight buffer coupled to the memory segment;
a logic circuit coupled to the memory segment and configured to generate intermediate data corresponding to input data and weight data read from the memory segment; and
a computation circuit coupled to the logic circuit and configured to, based on the intermediate data, generate output data corresponding to a computing-in-memory (CIM) operation using a first piece of weight data read from a first memory cell among a plurality of memory cells in the memory segment,
wherein the weight buffer is configured to, simultaneously with the CIM operation, update a second piece of weight data in a second memory cell among the plurality of memory cells in the memory segment, the second memory cell different from the first memory cell.
13 . The memory device of claim 12 , wherein
the weight buffer is configured to, simultaneously with the CIM operation using the first piece of weight data read from the first memory cell,
update the first piece of weight data in the first memory cell with a new first piece of weight data.
14 . The memory device of claim 13 , wherein
the weight buffer is configured to update the first piece of weight data in the first memory cell and the second piece of weight data in the second memory cell by providing the new first piece of weight data and a new second piece of weight data to the memory segment.
15 . The memory device of claim 12 , wherein
the weight buffer is configured to, simultaneously with the CIM operation using the first piece of weight data read from the first memory cell,
update at least one third piece of weight data in at least one third memory cell among the plurality of memory cells in the memory segment, the at least one third memory cell different from the first memory cell and the second memory cell.
16 . The memory device of claim 12 , further comprising:
a register configured to latch the first piece of weight data read from the first memory cell at an output of a register,
wherein the logic circuit is configured to generate the intermediate data corresponding to the input data and the latched first piece of weight data at the output of the register.
17 . The memory device of claim 16 , wherein
the plurality of memory cells in the memory segment comprises single-port memory cells coupled to a same bit line, and
the bit line is coupled to an input of the register.
18 . The memory device of claim 12 , wherein
the logic circuit is configured to perform a multiplication of the first piece of weight data with the input data, and
the computation circuit comprises an adder tree configured to receive a result of the multiplication.
19 . A memory device, comprising:
at least one memory segment;
a weight buffer coupled to the at least one memory segment;
a register having
an input coupled to the at least one memory segment, and
an output;
a logic circuit having
a first input coupled to the output of the register,
a second input configured to receive input data, and
an output; and
a computation circuit coupled to the output of the logic circuit,
wherein the logic circuit and the computation circuit are configured to perform a computing-in-memory (CIM) operation based on
the input data, and
weight data read out from the at least one memory segment and latched by the register.
20 . The memory device of claim 19 , wherein
the at least one memory segment comprises a plurality of memory segments, and
the weight buffer is configured to provide new weight data to a memory segment among the plurality of memory segments while a further memory segment among the plurality of memory segments is being read to supply the corresponding weight data stored in the further memory segment for the CIM operation.