Switching circuit
A switching controller generates control pulses for specifying on/off states of a first transistor and a second transistor. One end of a capacitor is coupled to a switching node. A constant voltage is applied to the other end of the capacitor via a rectifier element. A dead time controller controls a delay time between adjacent edges of the first control pulse and the second control pulse according to a sensing voltage across both ends of the capacitor.
1 . A switching circuit comprising:
a first transistor and a second transistor;
a switching node, wherein a high-level voltage occurs at the switching node during a period in which the first transistor is turned on and the second transistor is turned off, a low-level voltage occurs at the switching node during a period in which the first transistor is turned off and the second transistor is turned on, and a negative voltage occurs at the switching node during a period in which both the first transistor and the second transistor are turned off;
a capacitor structured such that a first end thereof is coupled to the switching node;
a rectifier element structured to apply a constant voltage to a second end of the capacitor;
a switching controller structured to generate a first control pulse and a second control pulse for specifying on/off states of the first transistor and the second transistor;
a first gate driver structured to drive the first transistor according to the first control pulse;
a second gate driver structured to drive the second transistor according to the second control pulse;
a dead time controller structured to control a delay time between edges of the first control pulse and the second control pulse according to a sensing voltage across both ends of the capacitor; and
a discharge circuit coupled to the capacitor, and structured to discharge a charge stored in the capacitor in a period in which the first transistor is turned on.
2 . The switching circuit according to claim 1 , wherein the dead time controller comprises a comparator structured to compare a voltage across both ends of the capacitor with a predetermined target voltage,
and wherein the dead time controller increases or decreases the delay time according to an output of the comparator.
3 . The switching circuit according to claim 1 , wherein the dead time controller feedback controls the delay time such that a voltage across both ends of the capacitor approaches a predetermined target voltage.
4 . The switching circuit according to claim 1 , wherein the dead time controller independently controls the delay time when the first transistor is turned on and the delay time when the second transistor is turned on.
5 . The switching circuit according to claim 1 , further comprising a transformer comprising a primary winding and a secondary winding,
wherein the first transistor is coupled to the primary winding,
wherein the second transistor is coupled to the secondary winding,
and wherein a connection node that couples the secondary winding and the second transistor is employed as the switching node.
6 . The switching circuit according to claim 1 , wherein the first transistor and the second transistor are coupled in series,
and wherein a connection node that couples the first transistor and the second transistor is employed as the switching node.
7 . A switching power supply comprising the switching circuit according to claim 1 .
8 . A control circuit for a switching power supply, wherein a switching circuit comprises:
a first transistor and a second transistor;
a switching node, wherein a high-level voltage occurs at the switching node during a period in which the first transistor is turned on and the second transistor is turned off, a low-level voltage occurs at the switching node during a period in which the first transistor is turned off and the second transistor is turned on, and a negative voltage occurs at the switching node during a period in which both the first transistor and the second transistor are turned off;
a capacitor structured such that a first end thereof is coupled to the switching node;
a rectifier element structured to apply a constant voltage to a second end of the capacitor;
a first gate driver structured to drive the first transistor according to a first control pulse;
a second gate driver structured to drive the second transistor according to a second control pulse; and
a discharge circuit structured to discharge a charge stored in the capacitor in a period in which the first transistor is turned on,
and wherein the control circuit comprises:
a switching controller structured to generate the first control pulse and the second control pulse for specifying on/off states of the first transistor and the second transistor; and
a dead time controller structured to control a delay time between adjacent edges of the first control pulse and the second control pulse according to a sensing voltage across both ends of the capacitor.
9 . A switching circuit comprising:
a first transistor and a second transistor;
a switching node, wherein a high-level voltage occurs at the switching node during a period in which the first transistor is turned on and the second transistor is turned off, a low-level voltage occurs at the switching node during a period in which the first transistor is turned off and the second transistor is turned on, and a negative voltage occurs at the switching node during a period in which both the first transistor and the second transistor are turned off;
a capacitor structured such that a first end thereof is coupled to the switching node;
a rectifier element structured to apply a constant voltage to a second end of the capacitor;
a switching controller structured to generate a first control pulse and a second control pulse for specifying on/off states of the first transistor and the second transistor;
a first gate driver structured to drive the first transistor according to the first control pulse;
a second gate driver structured to drive the second transistor according to the second control pulse;
a dead time controller structured to control a delay time of at least one from among the first gate driver and the second gate driver according to a sensing voltage across both ends of the capacitor; and
a discharge circuit coupled to the capacitor, and structured to discharge a charge stored in the capacitor in a period in which the first transistor is turned on.
10 . The control circuit according to claim 8 , wherein the dead time controller comprises a comparator structured to compare a voltage across both ends of the capacitor with a predetermined target voltage,
and wherein the dead time controller increases or decreases the delay time according to an output of the comparator.
11 . The control circuit according to claim 8 , wherein the dead time controller feedback controls the delay time such that a voltage across both ends of the capacitor approaches a predetermined target voltage.
12 . The control circuit according to claim 8 , wherein the dead time controller independently controls the delay time when the first transistor is turned on and the delay time when the second transistor is turned on.
13 . The control circuit according to claim 8 , further comprising a transformer comprising a primary winding and a secondary winding,
wherein the first transistor is coupled to the primary winding,
wherein the second transistor is coupled to the secondary winding,
and wherein a connection node that couples the secondary winding and the second transistor is employed as the switching node.
14 . The control circuit according to claim 8 , wherein the first transistor and the second transistor are coupled in series,
and wherein a connection node that couples the first transistor and the second transistor is employed as the switching node.
15 . A switching power supply comprising the control circuit according to claim 8 .
16 . A gate driver circuit for a switching power supply, wherein the switching power supply comprises:
a first transistor and a second transistor;
a switching node, wherein a high-level voltage occurs at the switching node during a period in which the first transistor is turned on and the second transistor is turned off, a low-level voltage occurs at the switching node during a period in which the first transistor is turned off and the second transistor is turned on, and a negative voltage occurs at the switching node during a period in which both the first transistor and the second transistor are turned off;
a capacitor structured such that a first end thereof is coupled to the switching node;
a rectifier element structured to apply a constant voltage to a second end of the capacitor; and
a switching controller structured to generate a control signal for specifying a duty cycle of each of the first transistor and the second transistor such that an electrical state of the switching power supply approaches a target state,
and wherein the gate driver circuit comprises:
a pulse generating unit structured to generate a first control pulse and a second control pulse each having a duty cycle that corresponds to the control signal;
a first gate driver structured to drive the first transistor according to the first control pulse;
a second gate driver structured to drive the second transistor according to the second control pulse;
a dead time controller structured to control a delay time between adjacent edges of the first control pulse and the second control pulse according to a sensing voltage across both ends of the capacitor; and
a discharge circuit structured to discharge a charge stored in the capacitor in a period in which the first transistor is turned on.
17 . The gate driver circuit according to claim 16 , wherein the dead time controller increases or decreases the delay time based on a comparison result between a predetermined target voltage and a voltage across both ends of the capacitor.
18 . The gate driver circuit according to claim 16 , wherein the dead time controller feedback controls the delay time such that a voltage across both ends of the capacitor approaches a predetermined target voltage.
19 . The gate driver circuit according to claim 16 , wherein the dead time controller independently controls the delay time when the first transistor is turned on and the delay time when the second transistor is turned on.
20 . The gate driver circuit according to claim 16 , further comprising a transformer comprising a primary winding and a secondary winding,
wherein the first transistor is coupled to the primary winding,
wherein the second transistor is coupled to the secondary winding,
and wherein a connection node that couples the secondary winding and the second transistor is employed as the switching node.
21 . The gate driver circuit according to claim 16 , wherein the first transistor and the second transistor are coupled in series,
and wherein a connection node that couples the first transistor and the second transistor is employed as the switching node.
22 . A switching power supply comprising the switching circuit according to claim 16 .