Power amplifier device having vertical die interconnect structure
A power amplifier device includes a transistor die with an elongated bondpad coupled to a terminal of an integrated transistor. The device also includes a substrate formed from a stack of alternating dielectric and patterned conductive layers. An elongated die contact is exposed at a first substrate surface and is attached to the elongated bondpad to provide a uniform connection between the die contact and the elongated bondpad. A vertical interconnect structure is connected to the die contact and extends towards the second substrate surface. A circuit includes passive component(s) coupled to the second substrate surface and to the vertical interconnect structure. An encapsulation material layer covers the passive component(s) and the second substrate surface. A plurality of device interconnects are coupled to the substrate, electrically coupled to the power transistor die, and exposed at a contact surface of the power amplifier device.
1 . A power amplifier device comprising:
a first device surface;
a second device surface opposite the first device surface;
a power transistor die that includes
a first die surface,
a second die surface opposite the first die surface,
a first bondpad that is exposed at the first die surface, wherein the first bondpad has a bondpad length that is elongated along a first axis that is parallel to the first die surface,
a conductive layer on the second die surface, and
an integrated transistor that includes a gate terminal, a drain terminal, and a source terminal, wherein one of the gate terminal and the drain terminal is electrically coupled within the power transistor die to the first bondpad at the first die surface, and the source terminal is electrically coupled within the power transistor die to the conductive layer on the second die surface;
a substrate formed from a stack of multiple dielectric layers and multiple patterned conductive layers in an alternating arrangement, and a plurality of conductive vias electrically coupling portions of the multiple patterned conductive layers, wherein the substrate is defined by a first substrate surface and a second substrate surface opposite the first substrate surface, and wherein the substrate includes
a first die contact that is exposed at the first substrate surface and elongated along a second axis that is parallel to the first axis, wherein the first die contact is attached to the first bondpad of the power transistor die to provide a uniform connection between the first die contact and the first bondpad along the bondpad length of the first bondpad, and
a vertical interconnect structure connected to the first die contact and extending from the first die contact towards the second substrate surface, wherein the vertical interconnect structure is located between the first and second substrate surfaces, and the vertical interconnect structure extends from the first die contact in a direction that is perpendicular to the first substrate surface;
a first circuit on the second substrate surface and including at least one passive component that is connected to substrate contacts that are exposed at the second substrate surface, wherein the substrate contacts and the first circuit are electrically coupled to the vertical interconnect structure; and
a plurality of device interconnects coupled to the substrate, wherein at least some of the plurality of device interconnects are electrically coupled to the gate and drain terminals of the power transistor die, at least one of the plurality of device interconnects is electrically coupled to the vertical interconnect structure, and each of the plurality of device interconnects have distal ends that are exposed at the second device surface.
2 . The power amplifier device of claim 1 , wherein:
the bondpad length of the first bondpad is at least five times greater than a bondpad width.
3 . A power amplifier device comprising:
a first device surface;
a second device surface opposite the first device surface;
a first power transistor die that includes
a first die surface,
a second die surface opposite the first die surface,
a first bondpad that is exposed at the first die surface, wherein the first bondpad has a bondpad length that is elongated along a first axis that is parallel to the first die surface,
a conductive layer on the second die surface, and
a first integrated transistor that includes a gate terminal, a drain terminal, and a source terminal, wherein one of the gate terminal and the drain terminal is electrically coupled within the power transistor die to the first bondpad at the first die surface, and the source terminal is electrically coupled within the power transistor die to the conductive layer on the second die surface;
a second power transistor die that includes
a second bondpad that is exposed at a contact surface of the second power transistor die, and
a second integrated transistor that includes a first terminal coupled to the second bondpad;
a substrate formed from a stack of multiple dielectric layers and multiple patterned conductive layers in an alternating arrangement, and a plurality of conductive vias electrically coupling portions of the multiple patterned conductive layers, wherein the substrate is defined by a first substrate surface and a second substrate surface opposite the first substrate surface, and wherein the substrate includes
a first die contact that is elongated along the first axis and exposed at the first substrate surface, wherein the first die contact is attached to the first bondpad of the first power transistor die to provide a uniform connection between the first die contact and the first bondpad along the bondpad length of the first bondpad,
a second die contact exposed at the first substrate surface and attached to the second bondpad, and
a vertical interconnect structure connected to the first die contact and extending from the first die contact toward the second substrate surface in a direction parallel to a second axis that is perpendicular to the first axis, wherein the vertical interconnect structure is located between the first and second substrate surfaces, and the vertical interconnect structure includes at least one via of the plurality of conductive vias interleaved with multiple conductive layer portions formed from the multiple patterned conductive layers;
a first circuit on the second substrate surface and including at least one passive component that is connected to substrate contacts that are exposed at the second substrate surface, wherein the substrate contacts and the first circuit are electrically coupled to the vertical interconnect structure; and
a plurality of device interconnects coupled to the substrate, wherein at least some of the plurality of device interconnects are electrically coupled to the gate and drain terminals of the power transistor die, at least one of the plurality of device interconnects is electrically coupled to the vertical interconnect structure, and each of the plurality of device interconnects have distal ends that are exposed at the second device surface.
4 . The power amplifier device of claim 3 , further comprising:
a first encapsulation material layer covering the at least one passive component and the second substrate surface and defining the first device surface.
5 . The power amplifier device of claim 1 , further comprising:
a first encapsulation material layer covering the at least one passive component and the second substrate surface and defining the first device surface.
6 . The power amplifier device of claim 5 , further comprising:
a second encapsulation material layer covering the power transistor die and the first substrate surface, wherein the second encapsulation material layer defines the second device surface.
7 . The power amplifier device of claim 1 , wherein the vertical interconnect structure comprises:
a stack of multiple elongated vias of the plurality of conductive vias; and
multiple elongated conductive layer portions formed from the multiple patterned conductive layers and interleaved with the multiple elongated vias.
8 . The power amplifier device of claim 7 , wherein the multiple elongated vias and the multiple elongated conductive layer portions are aligned along the second axis.
9 . The power amplifier device of claim 7 , further comprising:
an input/output (I/O) contact of the plurality of device interconnects; and
an I/O conductor with an elongated proximal end connected to one of the multiple elongated conductive layer portions of the vertical interconnect structure, and a distal end electrically coupled to the I/O contact, wherein the I/O conductor is formed from a same patterned conductive layer as the one of the multiple elongated conductive layer portions, and the I/O conductor extends in a direction that is perpendicular to the vertical interconnect structure and the I/O conductor electrically connects the I/O contact to the vertical interconnect structure.
10 . The power amplifier device of claim 9 , further comprising:
at least one impedance matching component electrically coupled along the I/O conductor between the vertical interconnect structure and the I/O contact.
11 . The power amplifier device of claim 1 , wherein the first circuit comprises:
a conductive path formed from portions of an uppermost patterned conductive layer, wherein the conductive path has a proximal portion that is electrically connected to the vertical interconnect structure, and a distal portion that is electrically connected to a first device interconnect of the multiple device interconnects; and
the at least one passive component coupled along the conductive path.
12 . The power amplifier device of claim 11 , wherein the proximal portion of the conductive path extends in a direction that is perpendicular to the vertical interconnect structure.
13 . The power amplifier device of claim 11 , wherein the proximal portion of the conductive path extends from an end of the one of the multiple elongated conductive layer portions in a direction parallel to the first axis.
14 . The power amplifier device of claim 11 , wherein the at least one passive component comprises:
a discrete inductor connected to the second substrate surface; and
a discrete capacitor connected to the second substrate surface in series with the discrete inductor.
15 . The power amplifier device of claim 11 , wherein the at least on passive component comprises:
a radial stub coupled along the conductive path and formed from one or more portions of the multiple patterned conductive layers.
16 . The power amplifier device of claim 11 , wherein:
the at least one passive component includes an inductance and a capacitor coupled in series along the conductive path to form a series inductor-capacitor (LC) circuit configured to perform a function selected from a harmonic termination circuit and a shunt-L circuit.
17 . The power amplifier device of claim 1 , wherein:
the second die surface is recessed below the second device surface; and
the power amplifier device further includes a thermal structure contacting the second die surface.
18 . The power amplifier of claim 3 , wherein:
the first bondpad is an output bondpad for the first power transistor die, and the first bondpad is electrically coupled to the drain terminal of the first integrated transistor; and
the second bondpad is an output bondpad for the second power transistor die, and the second terminal is a drain terminal of the second integrated transistor.
19 . The power amplifier device of claim 3 , wherein the vertical interconnect structure comprises:
a stack of multiple elongated vias of the plurality of conductive vias; and
multiple elongated conductive layer portions formed from the multiple patterned conductive layers and interleaved with the multiple elongated vias.
20 . The power amplifier device of claim 3 , further comprising:
an impedance inverter formed from a portion of one of the multiple patterned conductive layers and having a first end coupled to the first die contact and a second end coupled to the second die contact.
21 . The power amplifier device of claim 3 , wherein:
the first power transistor forms a portion of a peaking amplifier of a Doherty amplifier;
the second power transistor forms a portion of a carrier amplifier of the Doherty amplifier; and
the first die contact corresponds to a combining node of the Doherty power amplifier.
22 . The power amplifier device of claim 3 , wherein:
the first power transistor forms a portion of a carrier amplifier of a Doherty amplifier;
the second power transistor forms a portion of a peaking amplifier of the Doherty amplifier; and
the first die contact corresponds to a combining node of the Doherty power amplifier.