Bias block for biasing transistors exhibiting non-linearity when designed for linear operation
A bias block for providing a bias voltage includes a transistor having a control terminal, a first current terminal and a second current terminal. A voltage level at the control terminal determines a magnitude of current flowing between the first current terminal and the second current terminal. The first current terminal is coupled to a supply voltage via a first impedance and the second current terminal is coupled to a constant reference potential via a second impedance. The second current terminal provides the bias voltage. The bias block further includes a capacitor coupled between the control terminal and the second current terminal of the transistor.
1 . A bias block for providing a bias voltage at a bias node to a first transistor, said bias block comprising:
a first impedance;
a second transistor having a control terminal, a first current terminal and a second current terminal, wherein a voltage level at said control terminal determines a magnitude of current flowing between said first current terminal and said second current terminal,
said first current terminal being coupled to a supply voltage via said first impedance; and
a second impedance coupled between said second terminal and a constant reference potential,
wherein a junction of said second current terminal and said second impedance is said bias node providing said bias voltage to said first transistor,
wherein said bias block further comprises:
a first capacitor coupled between said control terminal and said second current terminal.
2 . The bias block of claim 1 , wherein said first current terminal is a drain terminal, said second current terminal is a source terminal, and said control terminal is a gate terminal.
3 . The bias block of claim 1 , wherein each of said first transistor and said second transistor is a pseudo High Electron Mobility Transistor (pHEMT).
4 . The bias block of claim 2 , further comprising:
a third transistor having a drain terminal coupled to said supply voltage via a temperature-compensation block, and a source terminal coupled to said constant reference potential;
a fourth transistor having a drain terminal coupled to said supply voltage via a fourth impedance, and a source terminal coupled to said constant reference potential via a fifth impedance,
wherein a control terminal of said third transistor is coupled to said source terminal of said fourth transistor,
wherein a drain terminal of said third transistor is coupled to the control terminal of said second transistor.
5 . The bias block of claim 4 , further comprising a second capacitor coupled between said drain terminal of said third transistor and said constant reference potential.
6 . The bias block of claim 5 , wherein said temperature-compensation block comprises:
a sixth impedance, a seventh impedance and a diode,
wherein a series combination of said sixth impedance and said seventh impedance is coupled between said supply voltage and said drain terminal of said third transistor,
wherein an anode terminal of said diode is coupled to said supply voltage, and a cathode terminal of said diode is coupled to a junction of said sixth impedance and said seventh impedance.
7 . The bias block of claim 2 , wherein said first capacitor has a non-linear capacitance that enables pre-distortion of a signal applied at said junction,
wherein said pre-distortion is designed to cancel non-linearity of a circuit when said circuit is biased by said bias voltage.
8 . The bias block of claim 2 , wherein said first capacitor causes said bias block to present a high impedance to a high-frequency signal applied at said junction.
9 . The bias block of claim 2 , wherein providing of said bias voltage at said source terminal of said second transistor causes said bias block to present a low impedance at DC at said junction,
wherein said junction provides a leakage current of said first transistor.
10 . A circuit comprising:
an amplifier comprising a first transistor, said first transistor having a first control terminal, a first current terminal and a second current terminal, said first control terminal being designed to receive a bias voltage and an input signal of time-varying magnitude, said first transistor to amplify said input signal to generate an amplified signal when said bias voltage is of a fixed magnitude; and
a bias block to generate said bias voltage at said first control terminal for said amplifier, wherein said bias block comprises:
a first impedance;
a second transistor having a second control terminal, a third current terminal and a fourth current terminal, wherein a voltage level at said second control terminal of said second transistor determines a magnitude of current flowing between said third current terminal of said second transistor and said fourth current terminal of said second transistor,
said third current terminal of said second transistor being coupled to said a supply voltage via said first impedance; and
a second impedance coupled between said fourth terminal and a constant reference potential,
wherein a junction of said fourth current terminal of said second transistor and said second impedance is said bias node providing said bias voltage.
11 . The circuit of claim 10 , wherein said amplifier further comprises:
a load coupled between said supply voltage and said first current terminal, and
a source impedance coupled between said second current terminal and said constant reference potential,
wherein said first transistor is a pseudo High Electron Mobility Transistor (pHEMT),
wherein said first transistor provides said amplified signal at said first current terminal of said first transistor,
wherein said bias block further comprises:
a first capacitor coupled between said second control terminal of said second transistor and said fourth current terminal of said second transistor.
12 . The circuit of claim 11 , wherein said third current terminal is a drain terminal, said fourth current terminal is a source terminal, and said second control terminal is a gate terminal,
wherein said second transistor is a pseudo High Electron Mobility Transistor (pHEMT),
wherein said amplifier is a low-noise amplifier (LNA) and each of said input signal and said amplified signal are radio-frequency (RF) signals.
13 . The circuit of claim 12 , wherein said bias block further comprises:
a third transistor having a drain terminal coupled to said supply voltage via a temperature-compensation block, and a source terminal coupled to said constant reference potential;
a fourth transistor having a drain terminal coupled to said supply voltage via a fourth impedance, and a source terminal coupled to said constant reference potential via a fifth impedance,
wherein a control terminal of said third transistor is coupled to said source terminal of said fourth transistor,
wherein a drain terminal of said third transistor is coupled to the control terminal of said second transistor.
14 . The circuit of claim 13 , wherein said bias block further comprises a second capacitor coupled between said drain terminal of said third transistor and said constant reference potential
wherein said temperature-compensation block comprises:
a sixth impedance, a seventh impedance and a diode,
wherein a series combination of said sixth impedance and said seventh impedance is coupled between said supply voltage and said drain terminal of said third transistor,
wherein an anode terminal of said diode is coupled to said supply voltage, and a cathode terminal of said diode is coupled to a junction of said sixth impedance and said seventh impedance.
15 . The circuit of claim 11 , wherein said first capacitor has a capacitance value that enables pre-distortion of a signal applied at said junction,
wherein said pre-distortion is designed to cancel non-linearity of said amplifier.
16 . A system comprising:
an antenna; and
a first transceiver comprising a transmitter portion and a receiver portion each coupled to said first duplexer, said first transceiver to transmit communication signals to a wireless medium via said first duplexer and said antenna, said first transceiver to also receive communication signals from said wireless medium via said first duplexer and said antenna,
wherein said receiver portion comprises:
a low-noise amplifier (LNA) comprising a first transistor, said first transistor having a first control terminal, a first current terminal and a second current terminal, said first control terminal being designed to receive a bias voltage, and an input signal of time-varying magnitude comprised in said communication signals, said first transistor to amplify said input signal to generate an amplified signal when said bias voltage is of a fixed magnitude; and
a bias block to generate said bias voltage at said first control terminal for said LNA,
wherein said bias block comprises:
a first impedance;
a second transistor having a second control terminal, a third current terminal and a fourth current terminal, wherein a voltage level at said second control terminal of said second transistor determines a magnitude of current flowing between said third current terminal of said second transistor and said fourth current terminal of said second transistor,
said third current terminal of said second transistor being coupled to a supply voltage via said first impedance; and
a second impedance coupled between said second terminal and a constant reference potential,
wherein a junction of said fourth current terminal of said second transistor and said second impedance is said bias node providing said bias voltage.
17 . The system of claim 16 , wherein said amplifier further comprises:
a load coupled between said supply voltage and said first current terminal, and
an impedance coupled between said second current terminal and said constant reference potential,
wherein said first transistor is a pseudo High Electron Mobility Transistor (pHEMT),
wherein said bias block further comprises:
a first capacitor coupled between said second control terminal of said second transistor and said fourth current terminal of said second transistor.
18 . The system of claim 17 , wherein said third current terminal, said fourth current terminal and said second control terminal of said second transistor are respectively a drain terminal, a source terminal, and a gate terminal,
wherein said second transistor is a pseudo High Electron Mobility Transistor (pHEMT),
wherein said bias block further comprises:
a third transistor having a drain terminal coupled to said supply voltage via a temperature-compensation block, and a source terminal coupled to said constant reference potential;
a fourth transistor having a drain terminal coupled to said supply voltage via a fourth impedance, and a source terminal coupled to said constant reference potential via a fifth impedance,
wherein a control terminal of said third transistor is coupled to said source terminal of said fourth transistor,
wherein a drain terminal of said third transistor is coupled to the control terminal of said second transistor.
19 . The system of claim 18 , wherein said bias block further comprises a second capacitor coupled between said drain terminal of said third transistor and said constant reference potential,
wherein said temperature-compensation block comprises:
a sixth impedance, a seventh impedance and a diode,
wherein a series combination of said sixth impedance and said seventh impedance is coupled between said supply voltage and said drain terminal of said third transistor,
wherein an anode terminal of said diode is coupled to said supply voltage, and a cathode terminal of said diode is coupled to a junction of said sixth impedance and said seventh impedance,
wherein said first capacitor has a non-linear capacitance value that enables pre-distortion of a signal applied at said junction,
wherein said pre-distortion is designed to cancel non-linearity of said amplifier.