IP Library › Granted Patent US 12,512,837
Granted Patent B2
US 12,512,837 · App. 18/008,176 · Granted Dec 30, 2025

System and method for forming radiation hardened circuitry

Inventors: Clayton Fullwood (Austin, TX); Timothy Hossain (Austin, TX)
Assignee: CERIUM LABORATORIES LLC
H03K19/0033G11C5/005H01L23/556
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Quick Facts
Patent No.
US 12,512,837
App. No.
18/008,176
Granted
Dec 30, 2025
Kind
B2
Abstract

A semiconductor component includes a substrate including a plurality of source/drain implants in the form of rows and a charge storage structure disposed over the substrate. The charge storage structure includes at least three continuous layers including a first silicon oxide layer, a silicon nitride layer disposed on the first silicon oxide layer, and a second silicon oxide layer disposed on the silicon nitride layer. The semiconductor component further includes a plurality of gate structures in the form of columns disposed over the charge structure and extending perpendicular to the rows and further includes a radiation protection layer disposed over the charge storage structure and the plurality of gate structures. The radiation protection layer includes a radiation resistant material including boron having an isotope composition of at least 90% boron-11.

Claims (31)

1 . A semiconductor component comprising:

a substrate including a plurality of source/drain implants in the form of rows;

a charge storage structure disposed over the substrate, the charge storage structure comprising at least three continuous layers including a first silicon oxide layer, a silicon nitride layer disposed on the first silicon oxide layer, and a second silicon oxide layer disposed on the silicon nitride layer, wherein the charge storage structure includes two charge storage regions disposed along each gate and between each pair of source/drain implants;

a plurality of gate structures in the form of columns disposed over the charge structure and extending perpendicular to the rows; and

a radiation protection layer disposed over the charge storage structure and the plurality of gate structures, the radiation protection layer including a radiation resistant material including boron having an isotope composition of at least 90% boron-11.

2 . The semiconductor component of claim 1 , wherein the isotope composition is at least 95% boron-11.

3 . The semiconductor component of claim 2 , wherein the isotope composition is at least 97% boron-11.

4 . The semiconductor component of claim 3 , wherein the isotope composition is at least 99% boron-11.

5 . The semiconductor component of claim 4 , wherein the isotope composition is at least 99.5% boron-11.

6 . The semiconductor component of claim 5 , wherein the isotope composition is at least 99.7% boron-11.

7 . The semiconductor component of claim 6 , wherein the isotope composition is at least 99.9% boron-11.

8 . The semiconductor component of claim 7 , wherein the isotope composition is at least 99.97% boron-11.

9 . The semiconductor component of claim 1 , wherein the radiation resistant material includes boron oxide, boron nitride, boron carbide, or a combination thereof.

10 . The semiconductor component of claim 9 , wherein the radiation resistant material is boron oxide.

11 . The semiconductor component of claim 9 , wherein the radiation resistant material is boron nitride.

12 . The semiconductor component of claim 1 , wherein the substrate is a p-type substrate.

13 . The semiconductor component of claim 12 , wherein the source/drain implants are n-type implants.

14 . The semiconductor component of claim 1 , wherein the plurality of gate structures includes polycrystalline silicon.

15 . The semiconductor component of claim 14 , wherein the polycrystalline silicon is a doped polycrystalline silicon.

16 . The semiconductor component of claim 1 , wherein the plurality of gate structures includes a silicide layer.

17 . The semiconductor component of claim 1 , wherein the substrate includes a buried radiation protection layer and a device layer disposed over the buried radiation protection layer, the plurality of source/drain implants disposed in the device layer and over the radiation protection layer.

18 . The semiconductor component of claim 17 , further comprising an insulator well disposed around the sides/edges of the buried radiation protection layer.

19 . A method for forming a semiconductor component, the method comprising:

implanting a set of source/drain rows in a substrate;

forming a continuous charge storage structure over the substrate and the set of source/drain rows;

forming a plurality of gate columns over the continuous charge storage structure, the gate columns extending perpendicular to the rows; and

depositing a radiation resistant material over the gate columns and the continuous charge storage structure, the radiation resistant material surrounding each gate column of the plurality of gate columns on at least three sides, the radiation resistant material including boron having an isotope composition of at least 90% boron-11.

20 . The method of claim 19 , wherein forming the continuous charge storage structure comprises:

forming a first silicon oxide layer;

forming a silicon nitride layer over the first silicon oxide layer; and

forming a second silicon oxide layer over the silicon nitride layer.

Continuity (2)
Provisional Application 63034876 · Jun 4, 2020
Related Publication 20230275585A1 · Aug 31, 2023
References Cited (4)
US 10840087B2 · Weimer · 2020 [cited by examiner]
US 20120043483A1 · Bowen, III · 2012 [cited by examiner]
US 20170205704A1 · Nikipelov · 2017 [cited by examiner]
US 20220206170A1 · Hossain · 2022 [cited by examiner]