Scheduling processing-in-memory requests and memory requests
A memory controller coupled to a memory module receives both processing-in-memory (PIM) requests and memory requests from a host (e.g., a host processor). The memory controller issues PIM requests to one group of memory banks and concurrently issues memory requests to one or more other groups of memory banks. Accordingly, memory requests are performed on groups of memory banks that would otherwise be idle while PIM requests are performed on the one group of memory banks. Optionally, the memory controller coupled to the memory module also takes various actions when switching between operating in a PIM mode and a non-processing-in-memory mode to reduce or hide overhead when switching between the two modes.
1 . A method comprising:
switching into a processing-in-memory mode which interleaves processing-in-memory requests and memory requests; and
in the processing-in-memory mode:
identifying one or more groups of memory banks of a processing-in-memory block that are idle while one or more processing-in-memory requests are being performed on the processing-in-memory block; and
issuing one or more memory requests on the one or more groups of memory banks that are idle while the one or more processing-in-memory requests are being performed on the processing-in-memory block.
2 . The method of claim 1 , further comprising:
determining a length of a processing-in-memory sequence that includes the one or more processing-in-memory requests; and
issuing, based at least in part on the length, one or more memory requests to the one or more groups of memory banks that are idle.
3 . The method of claim 1 , wherein the switching into the processing-in-memory mode is in response to determining that the one or more memory requests have a priority level above a predetermined threshold.
4 . The method of claim 1 , wherein the switching into the processing-in-memory mode is in response to determining that memory command latency restrictions allow for higher command bandwidth when processing-in-memory requests and memory requests are interleaved than when processing-in-memory requests alone are issued.
5 . The method of claim 1 , wherein the switching into the processing-in-memory mode is in response to determining that the one or more processing-in-memory requests are unable to fully utilize a memory command bus.
6 . The method of claim 1 , wherein the switching into the processing-in-memory mode is in response to determining that the one or more processing-in-memory requests will result in a first number of row buffer conflicts and a second number of row buffer hits, no more than the first number of memory requests that result in row buffer conflicts in the one or more groups of memory banks that are idle, and no more than the second number of memory requests that result in row buffer hits in the one or more groups of memory banks that are idle.
7 . The method of claim 1 , further comprising:
determining to switch from the processing-in-memory mode to a non-processing-in-memory mode; and
while a last one or more processing-in-memory requests are being performed, closing one or more rows in the one or more groups of memory banks that are idle and opening a row targeted by a next memory request to be executed in the non-processing-in-memory mode.
8 . The method of claim 7 , further comprising:
determining to switch from the non-processing-in-memory mode to the processing-in-memory mode; and
delaying closing one or more rows in the one or more groups of memory banks that are idle while at least one processing-in-memory request is performed on another one or more groups of memory banks of the processing-in-memory block.
9 . The method of claim 1 , wherein the method is implemented in a memory controller coupled to the processing-in-memory block.
10 . A system comprising:
a processing-in-memory block; and
a memory controller configured to:
switch into a processing-in-memory mode which interleaves processing-in-memory requests and memory requests; and
in the processing-in-memory mode:
identify one or more groups of memory banks of the processing-in-memory block that are idle while one or more processing-in-memory requests are being performed on the processing-in-memory block; and
issue one or more memory requests to the one or more groups of memory banks that are idle while the one or more processing-in-memory requests are being performed on the processing-in-memory block.
11 . The system of claim 10 , wherein the memory controller is further configured to:
determine a length of a processing-in-memory sequence that includes the one or more processing-in-memory requests; and
issue, based at least in part on the length, one or more memory requests to the one or more groups of memory banks that are idle.
12 . The system of claim 10 , wherein the memory controller is further configured to switch into the processing-in-memory mode in response to determining that the one or more memory requests have a priority level above a predetermined threshold.
13 . The system of claim 10 , wherein the memory controller is further configured to switch into the processing-in-memory mode in response to determining that memory command latency restrictions allow for higher command bandwidth when processing-in-memory requests and memory requests are interleaved than when processing-in-memory requests alone are issued.
14 . The system of claim 10 , wherein the memory controller is further configured to:
determine that the one or more processing-in-memory requests are unable to fully utilize a memory command bus; and
issue, in response to the one or more processing-in-memory requests being unable to fully utilize a memory command bus, the one or more memory requests to the one or more groups of memory banks that are idle.
15 . The system of claim 10 , wherein the memory controller is further configured switch into the processing-in-memory mode in response to determining that the one or more processing-in-memory requests will result in a first number of row buffer conflicts and a second number of row buffer hits, no more than the first number of memory requests that result in row buffer conflicts in the one or more groups of memory banks that are idle, and no more than the second number of memory requests that result in row buffer hits in the one or more groups of memory banks that are idle.
16 . The system of claim 10 , wherein the memory controller is further configured to:
determine to switch from the processing-in-memory mode to a non-processing-in-memory mode; and
while a last one or more processing-in-memory requests are being performed, close one or more rows in the one or more groups of memory banks that are idle and open a row targeted by a next memory request to be executed in the non-processing-in-memory mode.
17 . The system of claim 16 , wherein the memory controller is further configured to:
determine to switch from the non-processing-in-memory mode to the processing-in-memory mode; and
delay closing one or more rows in the one or more groups of memory banks that are idle while at least one processing-in-memory request is performed on another one or more groups of memory banks of the processing-in-memory block.
18 . A computing device comprising:
a memory controller configured to:
switch into a processing-in-memory mode which interleaves processing-in-memory request and memory requests by issuing one or more memory requests to one or more groups of memory banks that are idle while one or more processing-in-memory requests are being performed on a processing-in-memory block; and
switch from the processing-in-memory mode to a non-processing-in-memory mode; and
while a last one or more processing-in-memory requests are being performed, close one or more rows in one or more groups of memory banks that are idle and open a row targeted by a next memory request to be executed in the non-processing-in-memory mode.
19 . The computing device of claim 18 , wherein the memory controller is configured to switch between the processing-in-memory mode and a non-processing-in-memory mode based on priority levels of processing-in-memory requests and memory requests.
20 . The computing device of claim 18 , wherein the memory controller is configured to switch between the processing-in-memory mode and a non-processing-in-memory mode based on a number of processing-in-memory requests and memory requests.