Clock domain crossing verification with setup assistance
A computing system can perform static verification operations on a circuit design with a first set of design constraints characterizing portions of an electronic device described by the circuit design and identify one or more violations associated with clock domain crossings in the circuit design. The computing system can analyze the circuit design and the first set of the design constraints to determine at least one of the violations associated with the clock domain crossings in the circuit design corresponds to the first set of the design constraints, and generate one or more additional design constraints to integrate into the first set of the design constraints based on the analysis of the circuit design and the first set of the design constraints. The computing system can re-perform the static verification operations on the circuit design based on a second set of the design constraints that includes the additional design constraints.
1 . A method comprising:
identifying, by a computing system, one or more violations associated with clock domain crossings in a circuit design based, at least in part, on static verification operations performed on the circuit design with a set of design constraints characterizing portions of an electronic device described by the circuit design;
analyzing, by the computing system, the circuit design and the set of the design constraints by grouping clock signals in the circuit design into multiple asynchronous clock groups or by grouping the clock domain crossings in the circuit design based on a commonality of transmission registers for the clock domain crossings to determine at least one of the violations associated with the clock domain crossings in the circuit design corresponds to the set of the design constraints; and
generating, by the computing system, one or more additional design constraints to integrate into the set of the design constraints based on the asynchronous clock groups and the violations associated with the clock domain crossings in the circuit design or a presence of synchronizing circuitry utilized in the clock domain crossings for the groups and the violations associated with the clock domain crossings in the circuit design.
2 . The method of claim 1 , further comprising performing, by the computing system, static verification operations on the circuit design based, at least in part, on the set of the design constraints having been integrated with the additional design constraints.
3 . The method of claim 1 , further comprising consolidating the violations associated with at least one of the groups of the clock domain crossings into a single violation.
4 . The method of claim 1 , wherein analyzing the circuit design and the set of the design constraints further comprises analyzing input signals received by a reception register of a clock domain crossing, and wherein generating the one or more additional design constraints to report the input signals as a possible enable signal or to gray-code the input signals as a synchronized convergence.
5 . The method of claim 1 , wherein analyzing the circuit design and the set of the design constraints further comprises analyzing combinational logic driving synchronization circuitry in the clock domain crossing paths, and wherein generating the one or more additional design constraints based on which clock domain associated with the combinational logic.
6 . A system comprising:
a memory device configured to store machine-readable instructions; and
a computing system including one or more processing devices, in response to executing the machine-readable instructions, configured to:
identify one or more violations associated with clock domain crossings in a circuit design based, at least in part, on static verification operations performed on the circuit design with a set of design constraints characterizing portions of an electronic device described by the circuit design;
analyze the circuit design and the set of the design constraints by grouping clock signals in the circuit design into multiple asynchronous clock groups or by grouping the clock domain crossings in the circuit design based on a commonality of transmission registers for the clock domain crossings to determine at least one of the violations associated with the clock domain crossings in the circuit design corresponds to the set of the design constraints; and
generate one or more additional design constraints to integrate into the set of the design constraints based on the asynchronous clock groups and the violations associated with the clock domain crossings in the circuit design or a presence of synchronizing circuitry utilized in the clock domain crossings for the groups and the violations associated with the clock domain crossings in the circuit design.
7 . The system of claim 6 , wherein the one or more processing devices, in response to executing the machine-readable instructions, are further configured to perform static verification operations on the circuit design based, at least in part, on the set of the design constraints having been integrated with the additional design constraints.
8 . The system of claim 6 , wherein the one or more processing devices, in response to executing the machine-readable instructions, are further configured to consolidate the violations associated with at least one of the groups of the clock domain crossings into a single violation.
9 . The system of claim 6 , wherein the one or more processing devices, in response to executing the machine-readable instructions, are further configured to:
analyze the circuit design and the set of the design constraints by analyzing input signals received by a reception register of a clock domain crossing, and
generate the one or more additional design constraints to report the input signals as a possible enable signal or to gray-code the input signals as a synchronized convergence.
10 . An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
identifying, one or more violations associated with clock domain crossings in a circuit design based, at least in part, on static verification operations performed on the circuit design with a set of design constraints characterizing portions of an electronic device described by the circuit design;
analyzing the circuit design and the set of the design constraints by grouping clock signals in the circuit design into multiple asynchronous clock groups or by grouping the clock domain crossings in the circuit design based on a commonality of transmission registers for the clock domain crossings to determine at least one of the violations associated with the clock domain crossings in the circuit design corresponds to the set of the design constraints; and
generating one or more additional design constraints to integrate into the set of the design constraints based on the asynchronous clock groups and the violations associated with the clock domain crossings in the circuit design or a presence of synchronizing circuitry utilized in the clock domain crossings for the groups and the violations associated with the clock domain crossings in the circuit design.
11 . The apparatus of claim 10 , wherein the instructions are configured to cause the one or more processing devices to perform operations further comprising performing static verification operations on the circuit design based, at least in part, on the set of the design constraints having been integrated with the additional design constraints.
12 . The apparatus of claim 10 , wherein the instructions are configured to cause the one or more processing devices to perform operations further comprising consolidating the violations associated with at least one of the groups of the clock domain crossings into a single violation.
13 . The apparatus of claim 12 , wherein analyzing the circuit design and the set of the design constraints further comprises analyzing input signals received by a reception register of a clock domain crossing, and wherein generating the one or more additional design constraints to report the input signals as a possible enable signal or to gray-code the input signals as a synchronized convergence.
14 . The apparatus of claim 10 , wherein analyzing the circuit design and the set of the design constraints further comprises analyzing combinational logic driving synchronization circuitry in the clock domain crossing paths, and wherein generating the one or more additional design constraints based on which clock domain associated with the combinational logic.