IP Library Granted Patent US 12,526,983
Granted Patent B2
US 12,526,983 · App. 18/133,056 · Granted Jan 13, 2026

Semiconductor structure and method of manufacturing the same

Inventors: Yao-Hsiung Kung (Taoyuan, TW); Yu-Li Wu (New Taipei, TW); Shao-En Yeh (Taoyuan, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H10B12/33H10B12/05H10B12/488
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Quick Facts
Patent No.
US 12,526,983
App. No.
18/133,056
Granted
Jan 13, 2026
Kind
B2
Abstract

The present disclosure provides a semiconductor structure and a method of manufacturing a semiconductor structure. The semiconductor structure includes: a data storage unit in a first dielectric layer; a word line disposed over the data storage unit; an array of conductive pads disposed over the word line; a hard mask layer disposed over the array of conductive pads; and a second dielectric layer laterally surrounding the hard mask layer and the array of conductive pads, the second dielectric layer is leveled with the hard mask layer.

Claims (15)

1 . A semiconductor structure, comprising:

a data storage unit in a first dielectric layer;

a word line disposed over the data storage unit;

an array of conductive pads disposed over the word line;

a hard mask layer disposed over the array of conductive pads; and

a second dielectric layer laterally surrounding the hard mask layer and the array of conductive pads, the second dielectric layer is leveled with the hard mask layer,

wherein the array of conductive pads form a pattern following a pattern of the hard mask layer.

2 . The semiconductor structure of claim 1 , further comprising an antireflection coating over the hard mask layer.

3 . The semiconductor structure of claim 1 , further comprising a third dielectric layer over the second dielectric layer.

4 . The semiconductor structure of claim 3 , wherein the third dielectric layer is leveled with the second dielectric layer.

5 . The semiconductor structure of claim 3 , wherein the second dielectric layer fills a space between the array of conductive pads.

6 . The semiconductor structure of claim 3 , further comprising a plurality of channel layers extending through the word line.

7 . The semiconductor structure of claim 6 , further comprising an insulating film disposed between the word line and the plurality of channel layers.

8 . The semiconductor structure of claim 6 , wherein the plurality of channel layers comprise conductive oxide.

9 . The semiconductor structure of claim 6 , further comprising a conductive layer electrically coupling the data storage unit to one of the plurality of channel layers, wherein the conductive layer comprises oxide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2023
From: KUNG, YAO-HSIUNG; WU, YU-LI; YEH, SHAO-EN
To: NANYA TECHNOLOGY CORPORATION
Reel/Frame 063286/0416 →
Continuity (1)
Related Publication 20240349485A1 · Oct 17, 2024
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