Transistor source/drain regions and methods of forming the same
In an embodiment, a device includes: a semiconductor fin extending from a semiconductor substrate; a nanostructure above the semiconductor fin; a source/drain region adjacent a channel region of the nanostructure; a bottom spacer between the source/drain region and the semiconductor fin; and a gap between the bottom spacer and the source/drain region.
1 . A method comprising:
etching a source/drain recess in a first nanostructure, a second nanostructure, and a semiconductor fin;
recessing a sidewall of the second nanostructure in the source/drain recess to form a sidewall recess;
forming an inner spacer on the sidewall of the second nanostructure in the sidewall recess;
after forming the inner spacer, growing a semiconductor layer on a top surface of the semiconductor fin in the source/drain recess;
after growing the semiconductor layer, forming a bottom spacer on the semiconductor layer and in the source/drain recess; and
growing an epitaxial source/drain region in the source/drain recess, the epitaxial source/drain region grown from the first nanostructure.
2 . The method of claim 1 , wherein the epitaxial source/drain region fills an upper portion of the source/drain recess, a lower portion of the source/drain recess remaining unfilled by the epitaxial source/drain region to form a gap between the epitaxial source/drain region and the bottom spacer.
3 . The method of claim 2 , wherein the semiconductor layer is also grown on a sidewall of the semiconductor fin in the source/drain recess.
4 . The method of claim 1 , wherein forming the inner spacer comprises:
depositing a spacer layer in the sidewall recess and the source/drain recess; and
patterning the spacer layer to form the inner spacer.
5 . The method of claim 4 , further comprising:
forming a gate structure around the first nanostructure; and
forming a first gate spacer on a sidewall of the gate structure, wherein patterning the spacer layer forms a second gate spacer on a sidewall of the first gate spacer.
6 . The method of claim 4 , wherein patterning the spacer layer comprises etching the spacer layer with an isotropic wet etch performed using potassium hydroxide, tetramethylammonium hydroxide, or ethylenediamine pyrocatechol as an etchant.
7 . The method of claim 2 , wherein the semiconductor layer contacts a sidewall of the inner spacer.
8 . The method of claim 2 , wherein the semiconductor layer is doped to have a conductivity type opposite from a conductivity type of the epitaxial source/drain region.
9 . The method of claim 2 , wherein growing the semiconductor layer comprises growing the semiconductor layer until the semiconductor layer contacts insulating fins in the source/drain recess, wherein gaps are formed between the semiconductor layer and sidewalls of isolation regions beneath the insulating fins.
10 . The method of claim 2 , wherein growing the semiconductor layer comprises stopping growth of the semiconductor layer before the semiconductor layer contacts insulating fins in the source/drain recess.
11 . A method comprising:
forming a first spacer and a second spacer, the first spacer formed between a first nanostructure and a semiconductor fin, the second spacer formed between a second nanostructure and the semiconductor fin;
growing a semiconductor layer on a top surface of the semiconductor fin;
forming a third spacer on the semiconductor layer, the third spacer extending continuously across a top surface of the semiconductor layer and between the first spacer and the second spacer; and
growing an epitaxial source/drain region over the third spacer and between the first nanostructure and the second nanostructure, the epitaxial source/drain region being doped to have a conductivity type opposite from a conductivity type of the semiconductor layer.
12 . The method of claim 11 , wherein the semiconductor layer extends continuously across the top surface of the semiconductor fin and between the first spacer and the second spacer.
13 . The method of claim 11 , wherein the semiconductor layer is grown with a first growth process using an etchant-containing precursor, the epitaxial source/drain region is grown with a second growth process using the etchant-containing precursor, and the etchant-containing precursor is flowed at a greater flow rate during the first growth process than during the second growth process.
14 . The method of claim 11 , further comprising:
forming an insulating fin, the epitaxial source/drain region being grown until the epitaxial source/drain region contacts the insulating fin, the semiconductor layer being grown until the semiconductor layer contacts the insulating fin.
15 . The method of claim 11 , further comprising:
forming an insulating fin, the epitaxial source/drain region being grown until the epitaxial source/drain region contacts the insulating fin, growth of the semiconductor layer being stopped before the semiconductor layer contacts the insulating fin.
16 . The method of claim 11 , wherein growth of the epitaxial source/drain region is stopped so that a gap is formed between the epitaxial source/drain region and the third spacer.
17 . The method of claim 11 , wherein the semiconductor layer is grown on a sidewall of the semiconductor fin.
18 . The method of claim 11 , wherein the semiconductor layer is not grown on a sidewall of the semiconductor fin.
19 . A method comprising:
forming a source/drain recess in a semiconductor fin and in nanostructures stacked over the semiconductor fin;
growing a semiconductor layer in the source/drain recess to at least partially fill a portion of the source/drain recess in the semiconductor fin, the semiconductor layer having a flat top surface;
forming a bottom spacer extending continuously along the flat top surface of the semiconductor layer between opposing sidewalls of the source/drain recess;
growing an epitaxial source/drain region in the source/drain recess and over the bottom spacer;
forming an interlayer dielectric over the epitaxial source/drain region; and
forming a source/drain contact extending through the interlayer dielectric to contact the epitaxial source/drain region.
20 . The method of claim 19 , wherein growing the epitaxial source/drain region comprises growing the epitaxial source/drain region with a process that promotes semiconductor material growth from the nanostructures while suppressing growth from the bottom spacer.