IP Library Granted Patent US 12,532,529
Granted Patent B2
US 12,532,529 · App. 18/170,387 · Granted Jan 20, 2026

Semiconductor devices and methods of manufacturing thereof

Inventors: Jun-Ye Liu (Hsinchu, TW); Jih-Sheng Yang (Hsinchu, TW); Yu-Hsien Lin (Hsinchu, TW); Ryan Chia-Jen Chen (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H10D64/518H01L21/28088H01L21/28114H10D30/024H10D30/6211H10D64/017H10D64/667
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Quick Facts
Patent No.
US 12,532,529
App. No.
18/170,387
Granted
Jan 20, 2026
Kind
B2
Abstract

A method for fabricating semiconductor devices is disclosed. The method includes forming a gate trench over a semiconductor channel, the gate trench being surrounded by gate spacers. The method includes sequentially depositing a work function metal, a glue metal, and an electrode metal in the gate trench. The method includes etching respective portions of the electrode metal and the glue metal to form a gate electrode above a metal gate structure. The metal gate structure includes a remaining portion of the work function metal and the gate electrode includes a remaining portion of the electrode metal. The gate electrode has an upper surface extending away from a top surface of the metal gate structure.

Claims (34)

1 . A semiconductor device, comprising:

a semiconductor fin;

gate spacers over the semiconductor fin;

a metal gate structure, over the semiconductor fin, that is sandwiched by the gate spacers; and

a gate electrode disposed above and in electrical contact with the metal gate structure;

wherein the gate electrode extends away from a top surface of the metal gate structure and a top surface of the gate spacers.

2 . The semiconductor device of claim 1 , wherein the gate electrode includes tungsten.

3 . The semiconductor device of claim 1 , further comprising a glue metal vertically disposed between a bottom surface of the gate electrode and the top surface of the metal gate structure.

4 . The semiconductor device of claim 3 , wherein the glue metal and the gate electrode have their respective sidewalls aligned with each other.

5 . The semiconductor device of claim 4 , wherein the respective sidewalls of the glue metal and the gate electrode are further aligned with inner sidewalls of the gate spacers.

6 . The semiconductor device of claim 3 , wherein the glue metal has a bottom surface positioned above the top surface of the gate spacers.

7 . The semiconductor device of claim 1 , further comprising a glue metal with its sidewalls and a bottom surface enclosed by the metal gate structure.

8 . The semiconductor device of claim 7 , wherein sidewalls of the glue metal are spaced from each other with a first distance and sidewalls of the gate electrode are spaced from each other with a second distance, and wherein the second distance is substantially similar to the first distance.

9 . The semiconductor device of claim 7 , wherein a top surface of the glue metal is positioned above the top surface of the metal gate structure.

10 . A semiconductor device, comprising:

a semiconductor channel;

gate spacers over the semiconductor channel;

a metal gate structure, over the semiconductor channel, that is in contact with the gate spacers; and

a gate electrode disposed above and in electrical contact with the metal gate structure;

wherein the gate electrode extends away from a top surface of the metal gate structure and a top surface of the gate spacers.

11 . The semiconductor device of claim 10 , wherein the gate electrode consists essentially of tungsten.

12 . The semiconductor device of claim 10 , further comprising a glue metal between a bottom surface of the gate electrode and the top surface of the metal gate structure.

13 . The semiconductor device of claim 12 , wherein the glue metal and the gate electrode have coplanar sidewalls.

14 . The semiconductor device of claim 13 , wherein the coplanar sidewalls are further aligned with inner sidewalls of the gate spacers.

15 . The semiconductor device of claim 12 , wherein the glue metal has a bottom surface extending above the top surface of the gate spacers.

16 . The semiconductor device of claim 10 , further comprising a glue metal with its sidewalls and a bottom surface enclosed by the metal gate structure.

17 . The semiconductor device of claim 16 , wherein sidewalls of the glue metal are spaced from each other with a first distance and sidewalls of the gate electrode are spaced from each other with a second distance, and wherein the second distance is substantially similar to the first distance.

18 . The semiconductor device of claim 16 , wherein a top surface of the glue metal is positioned above the top surface of the metal gate structure.

19 . The semiconductor device of claim 10 , wherein the semiconductor channel is a fin extending from a semiconductive substrate.

20 . A semiconductor device comprising:

gate spacers over a plurality of semiconductor fins;

a metal gate structure sandwiched by the gate spacers; and

a gate electrode disposed above and in electrical contact with the metal gate structure;

wherein the gate electrode extends away from a top surface of the metal gate structure and a top surface of the gate spacers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2023
From: LIU, JUN-YE; YANG, JIH-SHENG; LIN, YU-HSIEN; CHEN, RYAN CHIA-JEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 062757/0161 →
Continuity (2)
Provisional Application 63410423 · Sep 27, 2022
Related Publication 20240105795A1 · Mar 28, 2024
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