IP Library Granted Patent US 12,532,541
Granted Patent B2
US 12,532,541 · App. 18/010,893 · Granted Jan 20, 2026

Display device

Inventors: Kang Young Lee (Yongin-si, KR); Chang Il Tae (Yongin-si, KR); Xinxing Li (Yongin-si, KR)
Assignee: Samsung Display Co., Ltd.
H10D86/60H01L25/167H10D86/471
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Quick Facts
Patent No.
US 12,532,541
App. No.
18/010,893
Granted
Jan 20, 2026
Kind
B2
Abstract

A display device includes a base layer including a display area and a non-display area, a pixel circuit layer disposed on a front surface of the base layer and including a driving transistor and a switch transistor, and an antistatic circuit layer disposed on a rear surface of the base layer and including at least one electrostatic diode.

Claims (56)

1 . A display device comprising:

a base layer including a display area and a non-display area;

a pixel circuit layer disposed on a front surface of the base layer and including a driving transistor and a switch transistor; and

an antistatic circuit layer disposed on a rear surface of the base layer and including an electrostatic diode.

2 . The display device according to claim 1 , wherein the electrostatic diode is disposed to overlap the display area in a thickness direction of the base layer.

3 . The display device according to claim 2 , further comprising:

a driver IC disposed on a rear surface of the antistatic circuit layer,

wherein a line of the driver IC is electrically connected to the electrostatic diode.

4 . The display device according to claim 1 , wherein the electrostatic diode is in a transistor form.

5 . The display device according to claim 4 , wherein the electrostatic diode is a bottom gate type.

6 . The display device according to claim 1 , further comprising: a via hole passing through the front surface and the rear surface of the base layer.

7 . The display device according to claim 6 , wherein

the pixel circuit layer further includes a connection electrode, and

the connection electrode is electrically connected to the electrostatic diode of the antistatic circuit layer through the via hole.

8 . The display device according to claim 1 , wherein a width of the non-display area is less than or equal to about 1 mm in a plan view.

9 . The display device according to claim 1 , further comprising:

a pixel emission layer disposed on a front surface of the pixel circuit layer and including a light emitting element.

10 . The display device according to claim 9 , wherein

the pixel emission layer further comprises:

a first electrode electrically connected to the driving transistor; and

a second electrode disposed to be spaced apart from the first electrode, and

the light emitting element is electrically connected to the first electrode and the second electrode.

11 . The display device according to claim 10 , wherein a length of the light emitting element is in a range of about 100 nm to about 10 μm.

12 . The display device according to claim 9 , further comprising:

a color conversion element layer disposed on the front surface of the pixel emission layer and including a quantum dot.

13 . The display device according to claim 1 , wherein the electrostatic diode includes an oxide semiconductor.

14 . The display device according to claim 3 , wherein the antistatic circuit layer includes a first electrostatic diode and a second electrostatic diode electrically connected in series with each other.

15 . The display device according to claim 14 , wherein

the first electrostatic diode includes:

a first gate electrode;

a first semiconductor pattern overlapping the first gate electrode in the thickness direction of the base layer; and

a first source/drain electrode and a second source/drain electrode, each electrically contacting the first semiconductor pattern, and

the second electrostatic diode includes:

a second gate electrode;

a second semiconductor pattern overlapping the second gate electrode in the thickness direction; and

the second source/drain electrodes and a third source/drain electrode, each electrically contacting the second semiconductor pattern.

16 . The display device according to claim 15 , wherein the first source/drain electrode and the third source/drain electrode are different portions of an electrode pattern.

17 . The display device according to claim 15 , wherein the first gate electrode and the second gate electrode are separated from each other.

18 . The display device according to claim 15 , wherein

the first source/drain electrode is electrically connected to a connection electrode disposed in the pixel circuit layer, and

the third source/drain electrode is electrically connected to the line of the driver IC.

19 . The display device according to claim 14 , wherein the first electrostatic diode and the second electrostatic diode are diode-connected transistors electrically connected in opposite directions.

20 . A display device comprising:

a base layer;

a pixel circuit layer disposed on the base layer and including a driving transistor and a switch transistor; and

an antistatic circuit layer including at least one an electrostatic diode and disposed in a direction different from a direction the pixel circuit layer is disposed.

21 . The display device according to claim 20 , further comprising:

a pixel emission layer including a light emitting element, and disposed in a direction different from of the direction the antistatic circuit layer is disposed.

22 . The display device according to claim 21 , wherein the electrostatic diode is disposed to overlap an emission area defined by the light emitting element in a thickness direction of the base layer.

23 . The display device according to claim 20 , wherein

the pixel circuit layer is disposed on a front surface of the base layer, and

the antistatic circuit layer is disposed on a rear surface of the base layer.

24 . The display device according to claim 23 , wherein the antistatic circuit layer is formed after the pixel circuit layer is formed.

25 . The display device according to claim 20 , further comprising:

a via hole passing through between a front surface and a rear surface of the base layer,

wherein the via hole is formed after the pixel circuit layer is formed and before the antistatic circuit layer is formed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2022
From: LEE, KANG YOUNG; TAE, CHANG IL; LI, XINXING
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 062127/0690 →
Priority Claims (1)
KR 10-2020-0074476 · Jun 18, 2020 · national
Continuity (1)
Related Publication 20230238402A1 · Jul 27, 2023
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