Jumper gate for advanced integrated circuit structures
Jumper gates for advanced integrated circuit structures are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowire segments. A second vertical stack of horizontal nanowire segments is spaced apart from the first vertical stack of horizontal nanowire segments. A conductive structure is laterally between and in direct electrical contact with the first vertical stack of horizontal nanowire segments and with the second vertical stack of horizontal nanowire segments. A first source or drain structure is coupled to the first vertical stack of horizontal nanowire segments at a side opposite the conductive structure. A second source or drain structure is coupled to the second vertical stack of horizontal nanowire segments at a side opposite the conductive structure.
1 . An integrated circuit structure, comprising:
a first vertical stack of horizontal nanowire segments;
a second vertical stack of horizontal nanowire segments spaced apart from the first vertical stack of horizontal nanowire segments;
a conductive structure laterally between and in direct electrical contact with the first vertical stack of horizontal nanowire segments and with the second vertical stack of horizontal nanowire segments;
a first source or drain structure coupled to the first vertical stack of horizontal nanowire segments at a side opposite the conductive structure; and
a second source or drain structure coupled to the second vertical stack of horizontal nanowire segments at a side opposite the conductive structure.
2 . The integrated circuit structure of claim 1 , wherein the conductive structure is vertically over a sub-fin structure.
3 . The integrated circuit structure of claim 1 , wherein the conductive structure has an uppermost surface above an uppermost surface of the first and second source or drain structures.
4 . The integrated circuit structure of claim 1 , wherein the first and second source or drain structures have a semiconductor material composition different than a semiconductor material composition of the first and second vertical stacks of horizontal nanowire segments.
5 . The integrated circuit structure of claim 4 , wherein the first and second source or drain structures comprise silicon and germanium, and the first and second vertical stacks of horizontal nanowire segments comprise silicon.
6 . A method of fabricating an integrated circuit structure, the method comprising:
forming vertical stack of horizontal nanowires;
cutting the vertical stack of horizontal nanowires to form a first vertical stack of horizontal nanowire segments, and a second vertical stack of horizontal nanowire segments spaced apart from the first vertical stack of horizontal nanowire segments;
forming a conductive structure laterally between and in direct electrical contact with the first vertical stack of horizontal nanowire segments and with the second vertical stack of horizontal nanowire segments;
forming a first source or drain structure coupled to the first vertical stack of horizontal nanowire segments at a side opposite the conductive structure; and
forming a second source or drain structure coupled to the second vertical stack of horizontal nanowire segments at a side opposite the conductive structure.
7 . The method of claim 6 , wherein the conductive structure is vertically over a sub-fin structure.
8 . The method of claim 6 , wherein the conductive structure has an uppermost surface above an uppermost surface of the first and second source or drain structures.
9 . The method of claim 6 , wherein the first and second source or drain structures have a semiconductor material composition different than a semiconductor material composition of the first and second vertical stacks of horizontal nanowire segments.
10 . The method of claim 9 , wherein the first and second source or drain structures comprise silicon and germanium, and the first and second vertical stacks of horizontal nanowire segments comprise silicon.
11 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure comprising:
a first vertical stack of horizontal nanowire segments;
a second vertical stack of horizontal nanowire segments spaced apart from the first vertical stack of horizontal nanowire segments;
a conductive structure laterally between and in direct electrical contact with the first vertical stack of horizontal nanowire segments and with the second vertical stack of horizontal nanowire segments;
a first source or drain structure coupled to the first vertical stack of horizontal nanowire segments at a side opposite the conductive structure; and
a second source or drain structure coupled to the second vertical stack of horizontal nanowire segments at a side opposite the conductive structure.
12 . The computing device of claim 11 , further comprising:
a memory coupled to the board.
13 . The computing device of claim 11 , further comprising:
a communication chip coupled to the board.
14 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.
15 . The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
16 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure fabricated according to a method comprising:
forming vertical stack of horizontal nanowires;
cutting the vertical stack of horizontal nanowires to form a first vertical stack of horizontal nanowire segments, and a second vertical stack of horizontal nanowire segments spaced apart from the first vertical stack of horizontal nanowire segments;
forming a conductive structure laterally between and in direct electrical contact with the first vertical stack of horizontal nanowire segments and with the second vertical stack of horizontal nanowire segments;
forming a first source or drain structure coupled to the first vertical stack of horizontal nanowire segments at a side opposite the conductive structure; and
forming a second source or drain structure coupled to the second vertical stack of horizontal nanowire segments at a side opposite the conductive structure.
17 . The computing device of claim 16 , further comprising:
a memory coupled to the board.
18 . The computing device of claim 16 , further comprising:
a communication chip coupled to the board.
19 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.
20 . The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.