Semiconductor structure
A semiconductor structure including a substrate and protection structures is provided. The substrate includes a die region. The die region includes corner regions. The protection structures are located in the corner region. Each of the protection structures has a square top-view pattern. The square top-view patterns located in the same corner region have various sizes.
1 . A semiconductor structure, comprising:
a substrate comprising a die region, wherein the die region comprises corner regions; and
protection structures located in the corner region, wherein each of the protection structures has a square top-view pattern, and the square top-view patterns located in the same corner region have various sizes,
wherein the die region further comprises a device region, and the corner regions are located outside the device region,
wherein a size relationship of two adjacent square top-view patterns is an increasing relationship in a direction away from the device region.
2 . The semiconductor structure according to claim 1 , wherein the protection structures comprise:
a first protection structure; and
a second protection structure located between the first protection structure and the device region.
3 . A semiconductor structure, comprising:
a substrate comprising a die region, wherein the die region comprises corner regions; and
protection structures located in the corner region, wherein each of the protection structures has a square top-view pattern, and the square top-view patterns located in the same corner region have various sizes,
wherein the die region further comprises a device region, and the corner regions are located outside the device region,
wherein the protection structures comprise:
a first protection structure; and
a second protection structure located between the first protection structure and the device region,
wherein the size of the square top-view pattern of the first protection structure is greater than the size of the square top-view pattern of the second protection structure.
4 . The semiconductor structure according to claim 2 , wherein the protection structures further comprise:
a third protection structure located between the second protection structure and the device region.
5 . A semiconductor structure, comprising:
a substrate comprising a die region, wherein the die region comprises corner regions; and
protection structures located in the corner region, wherein each of the protection structures has a square top-view pattern, and the square top-view patterns located in the same corner region have various sizes,
wherein the die region further comprises a device region, and the corner regions are located outside the device region,
wherein the protection structures comprise:
a first protection structure;
a second protection structure located between the first protection structure and the device region; and
a third protection structure located between the second protection structure and the device region,
wherein the size of the square top-view pattern of the first protection structure is greater than the size of the square top-view pattern of the second protection structure, and
the size of the square top-view pattern of the second protection structure is greater than the size of the square top-view pattern of the third protection structure.
6 . The semiconductor structure according to claim 1 , further comprising:
at least one seal ring structure located between the corner region and the device region.
7 . The semiconductor structure according to claim 6 , wherein the seal ring structure surrounds the device region.
8 . The semiconductor structure according to claim 6 , wherein a top-view shape of an edge profile of the seal ring structure comprises an octagon.
9 . The semiconductor structure according to claim 1 , further comprising:
dummy insertion structures located in an empty region of the device region.
10 . The semiconductor structure according to claim 1 , wherein two adjacent square top-view patterns have the same size.
11 . The semiconductor structure according to claim 1 , wherein a top-view shape of the corner region comprises a triangle.
12 . The semiconductor structure according to claim 1 , further comprising:
dummy insertion structures located in the corner region.
13 . The semiconductor structure according to claim 12 , wherein the dummy insertion structure is located between the protection structure and the device region.
14 . The semiconductor structure according to claim 12 , wherein a size of a top-view pattern of the dummy insertion structure is smaller than the size of the square top-view pattern of the protection structure.
15 . The semiconductor structure according to claim 1 , wherein the substrate further comprises a scribe line region, and the scribe line region is located outside the die region.
16 . The semiconductor structure according to claim 15 , further comprising:
dummy insertion structures located in an empty region of the scribe line region.
17 . The semiconductor structure according to claim 15 , further comprising:
an alignment mark located in the scribe line region.
18 . The semiconductor structure according to claim 17 , wherein the alignment mark is adjacent to the corner region.