Integrated circuit with backside metal gate cut for reduced coupling capacitance
An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor. The first and second nanostructure each include gate electrodes. A backside trench separates the first gate electrode from the second gate electrode. A bulk dielectric material fills the backside trench. A gate cap metal electrically connects the first gate electrode to the second gate electrode.
1 . An integrated circuit, comprising:
a first nanostructure transistor including a plurality of first semiconductor nanostructures and a first gate electrode surrounding the first semiconductor nanostructures;
a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second gate electrode surrounding the second semiconductor nanostructures;
a first backside gate isolation structure extending between the first gate electrode and the second gate electrode from a backside of the integrated circuit; and
a gate cap metal in contact with the first gate electrode, the second gate electrode, and the first backside gate isolation structure and electrically connecting the first gate electrode to the second gate electrode, wherein the first backside gate isolation structure has a substantially uniform first width between the first and second gate electrodes, wherein the first backside gate isolation structure has a second width that is smaller than the first width at a vertical level higher than the first and second gate electrodes.
2 . The integrated circuit of claim 1 , wherein the first backside gate isolation structure includes:
a first dielectric layer lining sidewalls of the first gate electrode, lining sidewalls of the second gate electrode, and in contact with the gate cap metal; and
a second dielectric layer on the first dielectric layer and filling a first trench between the first and second gate electrodes.
3 . The integrated circuit of claim 2 , comprising:
a third nanostructure transistor including a plurality of third semiconductor nanostructures and a third gate electrode surrounding the third semiconductor nanostructures, wherein the gate cap metal is in contact with the third gate electrode;
an interlevel dielectric layer over the first, second, and third semiconductor nanostructures;
a second trench between the second gate electrode and the third gate electrode and between the second semiconductor nanostructures and the third semiconductor nanostructures; and
a second backside gate isolation structure in the second trench including the first dielectric layer on sidewalls of the third gate electrode in the second trench and in contact with the interlevel dielectric layer at the second trench via a break in the gate cap metal at the second trench, wherein the first interlevel dielectric layer is separated from the interlevel dielectric layer by the gate cap metal at the first trench.
4 . The integrated circuit of claim 3 , wherein the second gate electrode is electrically isolated form the third gate electrode.
5 . The integrated circuit of claim 1 , wherein the first backside gate isolation structure includes a bulk dielectric layer in contact with sidewalls of the first and second gate electrodes and the gate cap metal.
6 . The integrated circuit of claim 5 , comprising:
a source/drain region of the first nanostructure transistor;
a backside conductive via extending through the bulk dielectric layer to the source/drain region;
an interlevel dielectric layer over the first nanostructure transistor; and
a source/drain contact extending through the interlevel dielectric layer to the source/drain region.
7 . An integrated circuit including:
a first nanostructure transistor including a first gate electrode;
a second nanostructure transistor including a second gate electrode;
a first backside trench separating the first gate electrode from the second gate electrode;
a dielectric liner layer lining sidewalls of the first gate electrode and the second gate electrode in the first backside trench;
a bulk dielectric layer on the dielectric liner layer and filling the first backside trench; and
a gate cap metal in contact with the first gate electrode, the second gate electrode and the dielectric liner layer at the first backside trench.
8 . The integrated circuit of claim 7 , comprising a backside hard mask having an opening, wherein the bulk dielectric layer is on a bottom surface of the backside hard mask and fills the first backside trench through the opening.
9 . The integrated circuit of claim 7 , comprising:
a third nanostructure transistor including a third gate electrode; and
a second backside trench separating the second gate electrode from the third gate electrode, wherein the dielectric liner layer lines sidewalls of the second gate electrode and the third gate electrode in the second backside trench, wherein the bulk dielectric layer fills the second backside trench.
10 . The integrated circuit of claim 7 , wherein the first nanostructure transistor includes a source/drain region.
11 . A device, comprising:
a first transistor including:
a plurality of stacked first channels:
a first gate electrode wrapped around the first channels;
a second transistor including:
a plurality of stacked second channels:
a second gate electrode wrapped around the second channels;
a first gate cap metal structure on a top surface of the first gate electrode;
a second gate cap metal structure on a top surface of the second gate electrode;
an interlevel dielectric layer above the first gate cap metal structure and the second gate cap metal structure;
a substrate below the first and second transistors;
a first trench extending through the substrate and between the first and second gate metals;
a first dielectric layer on sidewalls of the first gate metal and the second gate metal in the first trench and in contact with a side surface of the first gate cap metal structure and a side surface of the second gate cap meal structure.
12 . The device of claim 11 , further comprising a first bulk dielectric layer filling the trench in the substrate and between the first and second gate electrodes.
13 . The device of claim 12 , further comprising:
a third transistor including:
a plurality of stacked third channels:
a third gate electrode wrapped around the third channels, wherein the second gate cap metal structure is on a top surface of the third gate electrode.
14 . The device of claim 13 , further comprising:
a second trench extending through the substrate and between the second and third gate metals;
a second dielectric layer on sidewalls of the first gate metal and the second gate metal in the second trench and in contact with a bottom surface of the second gate cap metal structure.
15 . The device of claim 14 , wherein the first gate electrode and the second gate electrode are electrically isolated from each other.
16 . The device of claim 15 , wherein after the second gate cap metal structure electrically connects the second gate electrode and the third gate electrode.
17 . The device of claim 12 , wherein the first dielectric liner layer is in contact with the interlevel dielectric layer at the first trench.
18 . The device of claim 12 , wherein the first bulk dielectric material is separated from the interlevel dielectric layer by the first dielectric liner layer.
19 . The device of claim 18 , further comprising:
a source/drain region of the first transistor in contact with the first channels; and
a backside conductive via in contact with the source/drain region.
20 . The device of claim 12 , further comprising a backside hard mask on the substrate having an opening, wherein the first bulk dielectric layer is on a bottom surface of the backside hard mask and fills the first trench through the opening.