Single-photon avalanche diode with isolated junctions
The present disclosure relates to semiconductor structures and, more particularly, to a single-photon avalanche diode with isolated junctions and methods of manufacture. The structure includes a first p-n junction in a semiconductor material; and a second p-n junction in a second semiconductor material isolated from the first p-n junction by a buried insulator layer.
1 . A structure comprising:
a first p-n junction in a semiconductor material; and
a second p-n junction in a second semiconductor material isolated from the first p-n junction by a buried insulator layer;
a third p-n junction under the second p-n junction,
wherein the first p-n junction is isolated from the third p-n junction and the second p-n junction and the third p-n junction are not isolated from one another.
2 . The structure of claim 1 , wherein the first p-n junction is isolated from the second p-n junction by the buried insulator layer and shallow trench isolation structures.
3 . The structure of claim 2 , wherein the semiconductor material comprises a semiconductor on insulator substrate and the second semiconductor material comprises a bulk handle substrate.
4 . The structure of claim 3 , wherein the buried insulator layer comprises a buried oxide material between the semiconductor on insulator substrate and the bulk handle substrate.
5 . The structure of claim 3 , wherein the second p-n junction is under the first p-n junction.
6 . The structure of claim 3 , wherein the first p-n junction comprises a first single-photon avalanche diode and the second p-n junction comprises a second single-photon avalanche diode.
7 . The structure of claim 3 , wherein the first p-n junction comprises a P-well and an N+ diffusion in the semiconductor on insulator substrate and the second p-n junction comprises a deep N-well and a deep P-well in the bulk handle substrate.
8 . The structure of claim 7 , wherein the deep P-well comprises a high voltage deep P-well under a buried oxide layer of the semiconductor on insulator substrate.
9 . The structure of claim 1 , wherein the third p-n junction comprises the bulk handle substrate and the deep N-well in the bulk handle substrate.
10 . The structure of claim 1 , wherein the second p-n junction and the third p-n junction are vertically arranged.
11 . A structure comprising:
a first p-n junction in a semiconductor on insulator substrate;
a second p-n junction in a bulk semiconductor material under the first p-n junction;
a buried insulator layer isolating the first p-n junction from the second p-n junction;
a third p-n junction under the second p-n junction; and
shallow trench isolation structures which extend to the buried insulator layer and surround the first p-n junction,
wherein the first p-n junction is isolated and the second and third junction structures are not isolated from one another.
12 . The structure of claim 11 , wherein the first p-n junction is isolated from the second p-n junction by the buried insulator layer and the shallow trench isolation structures.
13 . The structure of claim 11 , wherein the first p-n junction further comprises a P-well wherein the first p-n junction comprises a portion of the P-well and N+ diffusion in the semiconductor on insulator substrate and the second p-n junction comprises a deep N-well and a deep P-well in a bulk substrate under the buried insulator layer.
14 . The structure of claim 13 , further comprising anode terminals connected to the P-well and cathode terminals connected to an N-well extended into the deep N-well and separated from the P-well by second shallow trench isolation structures.
15 . The structure of claim 13 , wherein the P-well further connects to ground terminals.
16 . The structure of claim 15 , wherein the P-well connected to the ground terminals are separated from the N-well connected to the cathode terminals by additional shallow trench isolation structures.
17 . The structure of claim 11 , wherein the third p-n junction isolated from the first p-n junction.
18 . A method comprising:
forming a first p-n junction in a semiconductor material; and
forming a second p-n junction in a second semiconductor material isolated from the first p-n junction; and
forming a third p-n junction under the second p-n junction,
wherein the first p-n junction is isolated from the third p-n junction and the second p-n junction and the third p-n junction are not isolated from one another.