Semiconductor device and method of forming dummy vias in WLP
A semiconductor device has a semiconductor substrate and first insulating layer formed over the surface of the semiconductor substrate. A dummy via is formed through the first insulating layer. A second insulating layer is formed over the first insulating layer to fill the dummy via. A first conductive layer is formed over the second insulating layer. A bump is formed over the first conductive layer adjacent to the dummy via filled with the second insulating layer. A second conductive layer is formed over a surface of the semiconductor substrate. The dummy via filled with the second insulating layer relieves stress on the second conductive layer. A plurality of dummy vias filled with the second insulating layer can be formed within a designated via formation area. A plurality of dummy vias filled with the second insulating layer can be formed in a pattern.
1 . A method of making a semiconductor device, comprising:
providing a semiconductor substrate;
forming a first conductive layer over a surface of the semiconductor substrate;
forming a first insulating layer over the surface of the semiconductor substrate and first conductive layer;
forming a dummy via through the first insulating layer and extending past the first conductive layer to the surface of the semiconductor substrate between a first portion of the first conductive layer and a second portion of the first conductive layer with no overlap between a vertical projection of the dummy via and the first conductive layer;
forming a second insulating layer over the first insulating layer to fill the dummy via; and
forming a second conductive layer over the second insulating layer and electrically connected to the first conductive layer.
2 . The method of claim 1 , further including forming a bump over the second conductive layer adjacent to the dummy via filled with the second insulating layer.
3 . The method of claim 1 , wherein the dummy via filled with the second insulating layer relieves stress on the first conductive layer.
4 . The method of claim 3 , further including forming a cutout in the first conductive layer.
5 . The method of claim 1 , further including forming a plurality of dummy vias filled with the second insulating layer within a designated via formation area.
6 . The method of claim 1 , further including forming a plurality of dummy vias filled with the second insulating layer in a pattern.
7 . A method of making a semiconductor device, comprising:
providing a semiconductor substrate;
forming a first conductive layer over a surface of the semiconductor substrate;
forming a first insulating layer over the surface of the semiconductor substrate and first conductive layer;
forming a dummy via through the first insulating layer and extending past the first conductive layer to the surface of the semiconductor substrate between a first portion of the first conductive layer and a second portion of the first conductive layer; and
forming a second insulating layer to fill the dummy via.
8 . The method of claim 7 , further including forming a bump over the second conductive layer adjacent to the dummy via filled with the second insulating layer.
9 . The method of claim 8 , further including forming a plurality of patterns of dummy vias filled with the second insulating layer adjacent to the bump.
10 . The method of claim 7 , wherein the dummy via filled with the second insulating layer relieves stress on the first conductive layer.
11 . The method of claim 10 , further including forming a cutout in the first conductive layer.
12 . The method of claim 7 , further including forming a plurality of dummy vias filled with the second insulating layer within a designated via formation area.
13 . The method of claim 7 , further including forming a plurality of dummy vias filled with the second insulating layer in a pattern.
14 . A semiconductor device, comprising:
a semiconductor substrate;
a first conductive layer formed over a surface of the semiconductor substrate;
a first insulating layer formed over the surface of the semiconductor substrate and first conductive layer;
a dummy via formed through the first insulating layer and extending past the first conductive layer to the surface of the semiconductor substrate between a first portion of the first conductive layer and a second portion of the first conductive layer with no overlap between a vertical projection of the dummy via and the first conductive layer;
a second insulating layer formed over the first insulating layer to fill the dummy via; and
a second conductive layer formed over the second insulating layer and electrically connected to the first conductive layer.
15 . The semiconductor device of claim 14 , further including a bump formed over the second conductive layer adjacent to the dummy via filled with the second insulating layer.
16 . The semiconductor device of claim 14 , wherein the dummy via filled with the second insulating layer relieves stress on the first conductive layer.
17 . The semiconductor device of claim 16 , further including a cutout formed in the first conductive layer.
18 . The semiconductor device of claim 14 , further including a plurality of dummy vias filled with the second insulating layer formed within a designated via formation area.
19 . The semiconductor device of claim 14 , further including a plurality of dummy vias filled with the second insulating layer formed in a pattern.
20 . A semiconductor device, comprising:
a semiconductor substrate;
a first conductive layer formed over a surface of the semiconductor substrate;
a first insulating layer formed over the surface of the semiconductor substrate and first conductive layer;
a dummy via formed through the first insulating layer and extending past the first conductive layer to the surface of the semiconductor substrate between a first portion of the first conductive layer and a second portion of the first conductive layer;
a second insulating layer filling the dummy via; and
a second conductive layer formed over the second insulating layer.
21 . The semiconductor device of claim 20 , further including a bump formed over the second conductive layer adjacent to the dummy via filled with the second insulating layer.
22 . The semiconductor device of claim 20 , wherein the dummy via filled with the second insulating layer relieves stress on the first conductive layer.
23 . The semiconductor device of claim 22 , further including a cutout formed in the first conductive layer.
24 . The semiconductor device of claim 20 , further including a plurality of dummy vias filled with the second insulating layer formed within a designated via formation area.
25 . The semiconductor device of claim 20 , further including a plurality of dummy vias filled with the second insulating layer formed in a pattern.
26 . A semiconductor device, comprising:
a substrate;
a first insulating layer formed over a surface of the substrate;
a dummy via formed through the first insulating layer and extending to the surface of the substrate;
a second insulating layer formed over the first insulating layer and extending into the dummy via; and
a first conductive layer formed over the second insulating layer.
27 . The semiconductor device of claim 26 , further including a bump formed over the first conductive layer adjacent to the dummy via filled with the second insulating layer.
28 . The semiconductor device of claim 26 , further including a second conductive layer formed over the surface of the substrate, wherein the second insulating layer within the dummy via relieves stress on the second conductive layer.
29 . The semiconductor device of claim 28 , further including a cutout formed in the second conductive layer.
30 . The semiconductor device of claim 26 , further including a plurality of dummy vias filled with the second insulating layer formed within a designated via formation area.
31 . The semiconductor device of claim 28 , wherein the dummy via extends past the second conductive layer to the surface of the substrate between a first portion of the second conductive layer and a second portion of the second conductive layer.
32 . The semiconductor device of claim 28 , wherein a vertical projection of the dummy via has no overlap with respect to the second conductive layer.
33 . The semiconductor device of claim 20 , wherein a vertical projection of the dummy via has no overlap with respect to the first conductive layer.